Browsing by Author "Chen, Bo-Yuan"

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Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs
(2018-10-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chen, Hsiu-Chih
Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs.
Comprehensive Noise Characterization and Modeling for 65-nm MOSFETs for Millimeter-Wave Applications
(2010-04-01)
Wang, Sheng-Chun
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Su, Pin
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Chen, Kun-Ming
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Liao, Kuo-Hsiang
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Chen, Bo-Yuan
Using an external tuner-based method, this paper demonstrates a complete millimeter-wave noise characterization and modeling up to 60 GHz for 65-nm MOSFETs for the first time. Due to channel length modulation, the channel noise continues to increase and remains the most important noise source in the millimeter-wave band. Our experimental results further show that, with the downscaling of channel length, the gate resistance has more serious impact on the high-frequency noise parameters than the substrate resistance even in the millimeter-wave frequency.
DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries
(2019-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Shiao, Yu-Shao Jerry
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Lin, Chuang-Ju
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Huang, Guo-Wei
In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f(T)) and maximum oscillation frequencies (f(max)) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f(T) and f(max) are around 25 GHz and 30 GHz, respectively. The high f(T) and f(m)(ax) as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications. (C) 2019 The Japan Society of Applied Physics
Design for integration of RF power transistors in 0.13 mu m advanced CMOS technology
(2007)
Huang, Sheng-Yi
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chang, Chun-Yen
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Hung, Cheng-Chou
An RF power MOSFET was proposed and manufactured in a standard 0.13 mu m CMOS technology. Without adding additional masks, cost and process, the breakdown voltage can be improved by using the N-well and shallow-trench-isolation processes to form a drift n(-) region. The breakdown voltage was 4.3V at gate bias of 1.2V. The cutoff frequency and maximum oscillation frequency were 68GHz and 87GHz, respectively. In addition, the power gain, output power and power-added efficiency were 16.8dB, 15.9dBm and 43.5%, respectively, at 2.4GHz. Good RF linearity also addressed OIP3 of 28.6dBm. The presented RF power transistor is cost effectively and can be applied into the power amplifier integration for RF SoC.
Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
(2015)
Lee, Yao-Jen
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Hou, Fu-Ju
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
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Kao, Kuo-Hsing
We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.
Effective Passivation With High-Density Positive Fixed Charges for GaN MIS-HEMTs
(2017-05-01)
Liu, Shih-Chien
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Huang, Chung-Kai
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Chang, Chia-Hua
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Lin, Yueh-Chin
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Chen, Bo-Yuan
An effective passivation with high-density positive fixed charges was demonstrated on GaN MIS-HEMTs. The positive fixed charges at the interface between passivation and AlGaN surface can reduce the surface potential and expand the quantum well under Fermi level. Besides, to satisfy charge balance, the net charge density at the AlGaN surface must equal to the 2DEG carrier density. Thus, the positive fixed charges passivation can increase the 2DEG carrier density and improve the switching performance of GaN MIS-HEMTs. In this paper, we demonstrated a high-density positive fixed charges (similar to 2.71 x 10(13) e/cm(-2)) passivation using SiON for GaN MIS-HEMTs. The device with SiON passivation exhibits significant improvements in I-V characteristics and dynamic R-ON compared to the conventional SiN passivated device.
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
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Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
GaN MIS-HEMTs With Nitrogen Passivation for Power Device Applications
(2014-10-01)
Liu, Shih-Chien
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Chen, Bo-Yuan
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Lin, Yueh-Chin
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Hsieh, Ting-En
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Wang, Huan-Chung
A GaN MIS-HEMT with nitrogen (N)-passivation for power device applications is demonstrated. In this letter, nitrogen radicals were adopted to recover nitrogen-vacancy-related defects which were formed due to the thermal decomposition and evaporation of nitrogen atoms from GaN surface during high-temperature process. Besides, nitrogen radicals can also remove impurities and reduce surface dangling bonds by forming Ga-N bonds on the SiN/GaN interface. With N-passivation, the device shows high ON/OFF current ratio, steep subthreshold slope, low OFF-state leakage current, high breakdown voltage, and improved dynamic ON-resistance. The device reliability under high-electric field stress was also improved as a result.
Ge/IIIV fin field-effect transistor common gate process and numerical simulations
(2017-04-01)
Chen, Bo-Yuan
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Chen, Jiann-Lin
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Chu, Chun-Lin
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Luo, Guang-Li
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Lee, Shyong
This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high-and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations. (C) 2017 Society of Photo-Optical Instrumentation Engineers (SPIE).
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High-frequency performances of superjunction laterally diffused metal-oxide-semiconductor transistors for RF power applications
(2016-04)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chang, Edward Yi
This paper presents the dc and high-frequency performances of laterally diffused metal-oxide-semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-mu m CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers. (C) 2016 The Japan Society of Applied Physics
High-frequency performances of superjunction laterally diffused metal-oxide-semiconductor transistors for RF power applications
(2016-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chang, Edward Yi
This paper presents the dc and high-frequency performances of laterally diffused metal-oxide-semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-mu m CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers. (C) 2016 The Japan Society of Applied Physics
Investigation of High-Frequency Noise Characteristics in Tensile-Strained nMOSFETs
(2011-03-01)
Wang, Sheng-Chun
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Su, Pin
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Chen, Kun-Ming
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Chen, Bo-Yuan
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Huang, Guo-Wei
For the first time, the high-frequency noise behavior of tensile-strained n-channel metal-oxide-semiconductor field-effect transistors, including their temperature dependency, is experimentally examined. Our experimental results show that with similar saturation voltages, the strained device is found to have larger channel noise than the control device at the same bias point. For given direct-current power consumption, however, due to enhanced transconductance, the strained device has better small-signal behaviors (higher f(t) and f(max)) and noise characteristics (smaller NF(min) and R(n)) than the control device.
Investigation of Hot-Carrier Stress Effect on High-Frequency Performance of Laterally Diffused Metal-Oxide-Semiconductor Transistors
(2012-02-01)
Chen, Kun-Ming
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Mou, Zong-Wen
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Kuo, Hao-Chung
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Chiu, Chia-Sung
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Chen, Bo-Yuan
The hot-carrier stress effects on the high-frequency performance characteristics of laterally diffused metal-oxide-semiconductor (LDMOS) transistors were investigated. A constant bias channel hot-carrier stress was applied at room temperature. After applying 3 h of hot-carrier stress, the on-resistance and saturation drain current degradations are 18 and 9%, respectively. However, the degradations of the cutoff frequency and maximum oscillation frequency were less than 2% when the devices were biased before the onset of quasi-saturation. In addition, we found that the degradations of high-frequency parameters are not related to the change in transconductance but to the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress were also examined in this study. The observations of S-parameter variations are important for RF power amplifier design. (C) 2012 The Japan Society of Applied Physics
Investigation of Temperature-Dependent High-Frequency Noise Characteristics for Deep-Submicrometer Bulk and SOI MOSFETs
(2012-03-01)
Wang, Sheng-Chun
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Su, Pin
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Chen, Kun-Ming
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Chen, Bo-Yuan
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Huang, Guo-Wei
The temperature dependence of high-frequency noise characteristics for deep-submicrometer bulk and silicon-on-insulator (SOI) MOSFETs has been experimentally examined in this paper. With the downscaling of the channel length, our paper indicates that the power spectral density of the channel noise (S-id) of the bulk MOSFET becomes less sensitive to temperature due to the smaller degradation of the channel conductance at zero drain bias g(d0) as temperature rises. We also show that the SOI-specific floating-body and self-heating effects would result in higher white-noise gamma factor. Finally, for both the bulk and SOI MOSFETs, since transconductance g(m) significantly decreases as temperature increases, their minimum noise figure NFmin and equivalent noise resistance R-n would degrade with increasing temperature.
LDMOS Transistor High-Frequency Performance Enhancements by Strain
(2012-04-01)
Chen, Kun-Ming
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Huang, Guo-Wei
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Chen, Bo-Yuan
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Chiu, Chia-Sung
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Hsiao, Chih-Hua
The effects of mechanical stress on the dc and high-frequency performances of laterally diffused MOS (LDMOS) transistors with different layout structures were investigated by using the wafer bending method. A 3.1% peak cutoff frequency (f(T)) enhancement is achieved for the multifinger device under 0.051% biaxial tensile strain. For LDMOS with annular layout, the f(T) enhancement is increased to 3.7% due to the various channel directions. Our results suggest the strain technology can be adopted in LDMOS for RF applications. The transconductance and gate capacitance were also extracted to clearly demonstrate the f(T) variations.
Low-Frequency Noise Characterization of AlGaN & x002F;GaN HEMTs and MIS-HEMTs Under UV Illumination
(2020-01-01)
Nagarajan, Venkatesan
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Chen, Kun-Ming
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Lin, Hsin-Yi
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Hu, Hsin-Hui
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Huang, Guo-Wei
The low-frequency noise characteristics of AlGaN & x002F;GaN HEMTs and MIS-HEMTs are investigated in the dark condition and under UV illumination. The test devices with a 3-& x03BC;m-thick GaN buffer and a 25-nm-thick Al_0.22Ga_0.78N barrier layer were fabricated on the silicon wafer. For MIS-HEMTs, a 25-nm-thick SiN layer was deposited as a gate dielectric. The measured low-frequency noises show a 1 & x002F;f spectrum and can be described by the carrier number fluctuation model. Different noise responses to the UV light between HEMTs and MIS-HEMTs were observed. By comparing the noise data in dark and under UV illumination, the noise sources under the gate and in the ungated gate-drain access region have been identified. From these results, we can find a design guideline to improve the noise and reliability of GaN-based devices for optoelectronic applications.
Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM
(2013)
Shen, Chang-Hong
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Shieh, Jia-Min
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Wu, Tsung-Ta
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Huang, Wen-Hsien
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Yang, Chih-Chao
For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.
Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs
(2019-01-01)
Hsueh, Fu-Kuo
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Lee, Chun-Ying
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Xue, Cheng-Xin
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Shen, Chang-Hong
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Shieh, Jia-Min
For the first time, below 400 degrees C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I-on/I-off ratio (similar to 10(8)) with low I-off (pFETs<10(-2) nA/mu m). Moreover, the stackability of the GAA MOSFETs and the differential output of dual-mode 10T SRAM readout enable 2x throughput in the CIM circuitry.