Browsing by Author "Chen, C"

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3-D simulation on current density distribution in flip-cbip solder joints with thick CuUBM under current stressing
(2005)
Liang, SW
;
Shao, TL
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Chen, C
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材料科學與工程學系
;
Department of Materials Science and Engineering
In flip-chip solder joints, Cu has been used as a under-bump metallization (UBM) for its excellent wettability with solders. In addition, electromigration has become an crucial reliability concerns for fine-pitch flip chip solder joints. In this paper, 3-D finite element method was employed to simulate the current density distribution for the eutectic SnPb solder joints with 5 mu m, 10 mu m, and 20 mu m thick Cu UBM. It was found that the thicker the UBM is, the lower the maximum current density inside the solder. The maximum current density decreased from 4.37 X. 10(4) A/cm(2) to 7.54 x 10(3) A/cm(2) when the thickness of the UBM changed from 5 gm to 20 mu m. Thicker Cu UBM can, effectively relieve the current crowding effect inside the solder.
A complete fault diagnostic system for automated vehicles operating in a platoon
(2001-07-01)
Rajamani, R
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Howell, AS
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Chen, C
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Hedrick, JK
;
Tomizuka, M
A "complete" fault diagnostic system is developed for automated vehicles operating as a platoon on an automated highway system. The diagnostic system is designed to monitor the complete set of sensors and actuators used by the lateral and longitudinal controllers of the vehicle, including radar sensors, magnetometers and inter-vehicle communication systems, A fault in any of the twelve sensors and three actuators is identified without requiring any additional hardware redundancy. The diagnostic system uses parity equations and several reduced-order nonlinear observers constructed from a simplified dynamic model of the vehicle. Nonlinear observer design techniques are used to guarantee asymptotically stable convergence of estimates for the nonlinear dynamic system. Different combinations of the observer estimates and the available sensor measurements are then processed to construct a bank of residues. The paper analytically shows that a fault in any one of the sensors or actuators creates a unique subset of these residues to grow so as to enable exact identification of the faulty component. Both simulation and experimental results are presented to demonstrate the effectiveness of the fault diagnostic system in the presence of various faults.
A fault-tolerant object service on CORBA
(1999-11-01)
Liang, D
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Fang, CL
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Yuan, SM
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Chen, C
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Jan, GE
The Common Object Request Broker Architecture (CORBA), is a major industrial standard for distributed object-based applications. Today's large-scale CORBA applications have to deal with object crashes, node failures, networks partitioning and unpredictable communication delays. Existing efforts to enhance the CORBA reliability can be roughly categorized into three approaches: integration approach, interception approach and service approach. Each approach has its own merits and prices. In this paper, we propose a service approach solution called Object Fault-tolerance Service (OFS). Solutions that adopt the service approach usually specify their service in terms of CORBA IDL interfaces. The implementations of such solutions in general do not modify the ORE infrastructure or IDL language mappings, and thus applications developed with those systems appear to be more portable. OFS differs from other service approach solutions in that OFS does not assume underlying support of reliable group communication. Applications with advance registration can rely on OFS for detection of object and node crashes, and for customized recovery. In this paper, we first present the service specification of OFS. We then give the system architecture of an OFS implementation. This OFS implementation is developed on the Solaris 2.5 platform and with IONA's Orbix 2.0. The performance evaluation of the OFS implementation is also presented. The preliminary experiments indicate that OFS overhead is minimal and client objects experience little response delay when a service object is under OFS surveillance. (C) 1999 Elsevier Science Inc. All rights reserved.
A loop partition technique for reducing cache bank conflict in multithreaded architecture
(1996-01-01)
Wu, CC
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Chen, C
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交大名義發表
;
資訊工程學系
;
National Chiao Tung University
Parallel multithreaded architectures take advantage of the ability to execute more than one thread simultaneously on a single chip at low synchronisation and communication costs and high hardware resource utilisation. However, a high bandwidth cache, such as a multibank cache, is especially critical to serve memory accesses issued at the same time from different threads. To prevent bank conflicts of multibank cache from seriously degrading system performance, a loop partition method is proposed to reduce or even eliminate bank conflicts. The partition allows each thread access to certain bank modules and prevents any two from accessing the same bank module. The method neither slows down the clock rate nor increases the array subscript expression complexity. The performance gains of the bank-conflict-free loop partition approach are shown in simulation results.
A new relaxed memory consistency model for shared-memory multiprocessors with parallel-multithreaded processing elements
(1998-12-01)
Wu, CC
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Chen, C
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資訊工程學系
;
Department of Computer Science
The release consistency model is the generally accepted hardware-centric relaxed memory consistency model because of its performance and implementation complexity. By extending the release consistency model, in this paper. we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessor systems with parallel-multithreaded processing elements. The new model uses a new categorization for memory references and utilizes the feature of parallel multithreaded processors (PMPs). We further partition acquire and release references into three sub-categories: one for lock-unlock pairs, one for barrier synchronization, and the last for others. According to the semantic of each synchronization primitive, each sub-category has its own relaxed restrictions. On the other hand, the feature of a PMP is that it is capable of executing more than one thread at the same time, where all parallel threads share only one cache hierarchy. Under the new model, we can use dual write-caches to reduce write traffic and synchronization time. We have used five benchmarks in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, the new model is superior to the release consistency model at best by about 11%.
A new scheduling strategy for NUMA multiprocessor systems
(1996)
Lai, GJ
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Chen, C
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資訊科學與工程研究所
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Institute of Computer Science and Engineering
A performance study of cache coherence protocols and write coaches for parallel-multithreaded shared-memory multiprocessors
(1998-01-01)
Wu, CC
;
Chen, C
;
資訊工程學系
;
Department of Computer Science
According to published research results, no directory-based cache coherence protocol provides best performance for all application programs in conventional multiprocessor systems that use sequential consistency models. However, recently it has been claimed that competitive-update protocols are superior to other protocols under a relaxed consistency model. Moreover, incorporating write caches improves the system performance of clean and competitive-update protocols. In this paper, we examine the different effects that occur when processing elements are replaced by parallel-multithreaded processors. According to our simulation results, the clean protocol provided the best performance for five out of six SPLASH programs. After augmentation with write caches, the clean protocol outperformed others for all applications. Though competitive-update protocols have been improved, their performance is not better than that of write-invalidate protocols for most programs.
A performance study of cache coherence protocols and write coaches for parallel-multithreaded shared-memory multiprocessors
(1998-01-01)
Wu, CC
;
Chen, C
;
資訊工程學系
;
Department of Computer Science
According to published research results, no directory-based cache coherence protocol provides best performance for all application programs in conventional multiprocessor systems that use sequential consistency models. However, recently it has been claimed that competitive-update protocols are superior to other protocols under a relaxed consistency model. Moreover, incorporating write caches improves the system performance of clean and competitive-update protocols. In this paper, we examine the different effects that occur when processing elements are replaced by parallel-multithreaded processors. According to our simulation results, the clean protocol provided the best performance for five out of six SPLASH programs. After augmentation with write caches, the clean protocol outperformed others for all applications. Though competitive-update protocols have been improved, their performance is not better than that of write-invalidate protocols for most programs.
A practical nonblocking queue algorithm using compare-and-swap
(2000)
Shann, CH
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Huang, TL
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Chen, C
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資訊工程學系
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Department of Computer Science
Many nonblocking algorithms have been proposed for shared queues. Previous studies indicate that link-based algorithms perform best. However, these algorithms have a memory management problem. a dequeued node can not be freed or reused without problem: handling. The problem is usually overloaded; one just assumes the existence of a lower level mechanism, which takes care of all the details of handling the problem. Employing such a mechanism incurs significant overheads, and consequently the link-based queues may not perform as well as claimed. A new nonblocking queue algorithm based on a finite array is proposed in this paper. Comparing with the link-based algorithms. the nerv algorithm provides the same degree of concurrency without being subject to the memory problem, hence suggests a good performance.
A reinforcement learning control scheme for nonlinear systems with multiple actions
(1996)
Chen, C
;
Jou, CC
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
In this paper an attempt is made to apply reinforcement learning schemes to the adaptive control of nonlinear systems with multiple continuous control actions. The control task is formulated into a sequential optimization problem. a learning algorithm is developed based on the concepts of dynamic programming and stochastic approximation and the techniques of random search and parameter estimation. The proposed algorithm is complete and general enough so that the controller can be constituted by various computing models, e.g., neural networks. The efficiency of the proposed algorithm is demonstrated by applying the methods to the nonlinear control problems with mutiple control actions.
A release combined scheduling scheme for non-uniform dependence loops
(2002-03-01)
Pean, DL
;
Chua, HT
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Chen, C
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資訊工程學系
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Department of Computer Science
In general, synchronization mechanisms can be used to preserve dependence constraints in any nested loop, and can be combined with a loop scheduling scheme to form a uniform framework to obtain the correct execution order and balance workload distribution. Most current scheduling mechanisms cannot handle non-uniform dependence loops. In this paper, we propose a new combined scheduling scheme called Release Combined Scheduling for Non-uniform Dependence Loops (RCS) to schedule non-uniform dependence doubly-nested loops in multiprocessor systems. It combines both static and dynamic scheduling mechanisms in order to optimize the system performance. In our approach, initialisation of a set of scheduling information is based on the concept of the minimum dependence distance. During runtime, scheduling information is used to adjust the number of parallelizable iterations. Our method is able to discover more parallelism from a given non-uniform dependence doubly-nested loop than is possible with previous approaches. The experimental results show that the RCS method reliably exploits parallelism and outperforms most of the existing non-uniform dependence loop scheduling schemes by 20.29%, on average.
A two-level scheduling method: an effective parallelizing technique for uniform nested loops on a DSP multiprocessor
(2005-02-15)
Lee, YH
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Chen, C
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資訊工程學系
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Department of Computer Science
A digital signal processor (DSP), which is a special-purpose microprocessor, is designed to achieve higher performance on DSP applications. Because most DSP applications contain many nested loops and permit a very high degree of parallelism, the DSP multiprocessor has a suitable architecture to execute these applications. Unfortunately, conventional scheduling methods used on DSP multiprocessors allocate only one operation to each DSP every time unit, even if the DSP includes several function units that can operate in parallel. Obviously they cannot achieve full function unit utilization. Hence, in this paper, we propose a two-level scheduling method (TSM) to overcome this common failing. TSM contains two approaches, which integrates unimodular transformations, loop tiling technique, and conventional methods used on single DSP, Besides introducing algorithm, we also use an analytic module to analyze its preliminary performance. Based on our analyses the TSM can achieve shorter execution time and more scalable speedup results. In addition, the TSM causes less memory access and synchronization overheads, which are usually negligible in the DSP multiprocessor architecture. (C) 2004 Elsevier Inc. All rights reserved.
Abnormal and regioselective Wacker oxidation of 1,5-dienes
(2003-09-01)
Ho, TL
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Chang, MH
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Chen, C
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應用化學系
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Department of Applied Chemistry
The presence of an additional double bond can change the regioselectivity of the Wacker oxidation of a 1-alkene moiety to give the aldehyde product. (C) 2003 Published by Elsevier Ltd.
Aging influence of poly(ethylene glycol) suppressors of Cu electrolytes on gaps filling
(2006-05-01)
Liu, SH
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Li, TC
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Chen, C
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Shieh, JM
;
Dai, BT
In this study, we investigate how the degradation of poly(ethylene glycol) (PEG) additives in Cu electroplating electrolytes influences the gaps filling of damascene features and the roughness of plated surfaces. The cleavage of PEG, whose reaction is enhanced by a high bias current and more plating cycles, not only diminishes the inhibition effect of the electrolytes, but also enables the formation of enormous complexes of short-chain PEG-Cu far from the reacting surfaces. Hence, the more plating cycles performed, the worse the gaps filling characteristic and the rougher the plated surfaces. Furthermore, an overshoot phenomenon on the transient cells voltage for PEG-containing electrolytes is observed and explained well by a dynamic equilibrium between PEG absorption ability and Cu reduction speed. Accordingly, the change in overshoot shape is closely related to PEG aging and this fact is employed to examine the reliability of electrolytes.
An effect scheme for fixed-length tunnel allocation in hierarchical WDM networks
(2005)
Lo, TY
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Chen, C
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Chen, YY
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資訊工程學系
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Department of Computer Science
In this paper, we investigate the static tunnel allocation problem in multigraularity optical cross-connect (MG-OXC) networks. Our goal is to allocate a set of tunnels that minimize the blocking probability for the dynamic traffic that will follow the prior-known historical traffic matrix. A heuristic Capacity-Balanced Static Tunnel Allocation (CB-STA) has been proposed [1], which always tries to allocate a tunnel from the node with maximal predicted traffic going out to the node with maximal predicted traffic coming in. However, the tunnel length constraint is not carefully considered while selecting node pairs. Thus, this work proposes a heuristic, Weighted Tunnel Allocation (WTA), to improve CB-STA. WTA adds some additional edges with predefined hop length, termed auxiliary links, to the original topology to form an auxiliary graph. Node pair incident to an auxiliary link means that there could be tunnels allocated for it. By routing the historical traffic on the auxiliary graph, preference of tunnel allocation for each node pair incident to the auxiliary link can be estimated. Finally the tunnels will be allocated according to the preference, The simulation results show that WTA outperforms CB-STA in all switching type combinations.
An optimized dependence convex hull partitioning technique to maximize parallelism of nested loops with non-uniform dependences
(2000)
Pean, DL
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Lai, GJ
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Chen, C
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資訊工程學系
;
Department of Computer Science
There are many methods existing for nested loop partitioning; however most of them perform poorly when partitioning loops with non-uniform dependences. This paper proposes a generalized and optimized loop partitioning mechanism to exploit parallelism from nested loops with non-uniform dependences. Our approach based on the dependence convex theory will divide the loop into variable size partitions. Furthermore, the proposed algorithm partitions a nested loop by using the copy-renaming and the optimized partitioning techniques to minimize the number of parallel regions of the iteration space, outperforming the other previous partition mechanisms of nested loops with non-uniform dependences.
An optimized three region partitioning technique to maximize parallelism of nested loops with non-uniform dependences
(2001-05-01)
Pean, DL
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Chen, C
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資訊工程學系
;
Department of Computer Science
There are many methods for nested loop partitioning exist: however. most of them perform poorly when they partition loops with non-uniform dependences. This paper proposes a generalized and optimized loop partitioning mechanism which can exploit parallelism in nested loops with non-uniform dependences. Our approach based on the region partitioning technique divides the loop into variable size partitions. Furthermore, the proposed algorithm partitions a nested loop using the copy-renaming and optimized partitioning techniques so as to minimize the serial part of the iteration space. Thus, it out performs previous partition mechanisms for nested loops with non-uniform dependences. Compared with other popular techniques, our scheme shows dramatic improve ment in preliminary performance results.
Critical length of electromigration for eutectic SnPb solder stripe
(2006-05-01)
Wei, CC
;
Chen, C
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材料科學與工程學系
;
Department of Materials Science and Engineering
The critical length of eutectic SnPb solder was investigated using solder stripes. By employing focus ion beam, solder stripes of various lengths, including 5, 10, 15, 20, 30, 100, and 200 mu m, can be fabricated. Length-dependent electromigration behavior was observed, which implies that there may be back stress under stressing. The critical length was determined to be between 10 and 15 mu m under stressing by 2x10(4) A/cm(2) at 100 degrees C, and the corresponding critical product was between 20 and 30 A/cm. Both values show good agreement with their theoretical values. (c) 2006 American Institute of Physics.
Cross interactions on interfacial compound formation of solder bumps and metallization layers during reflow
(2004-12-01)
Shao, TL
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Chen, TS
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Huang, YM
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Chen, C
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材料科學與工程學系
While the dimension of solder bumps keeps shrinking to meet higher performance requirements, the formation of interfacial compounds may be affected more profoundly by the other side of metallization layer due to a smaller bump height. In this study, cross interactions on the formation of intermetallic compounds (IMCs) were investigated in eutectic SnPb, SnAg3.5, SnAg3.8Cu0.7, and SnSb5 solders jointed to Cu/Cr-Cu/Ti on the chip side and Au/Ni metallization on the substrate side. It is found that the Cu atoms on the chip side diffused to the substrate side to form (Cu-x,Ni1-x)(6)Sn-5 or (Ni-y,Cu1-y)(3)Sn-4 for the four solders during the reflow for joining flip chip packages. For the SnPb solder, Au atoms were observed on the chip side after the reflow, yet few Ni atoms were detected on the chip side. In addition, for SnAg3.5 and SnSn5 solders, the Ni atoms on the substrate side migrated to the chip side during the reflow to change binary Cu6Sn5 into ternary (Cu-x,Ni1-x)(6)Sn-5 IMCs, in which the Ni weighed approximately 21%. Furthermore, it is intriguing that no Ni atoms were detected on the chip side of the SnAg3.8Cu0.7 joint. The possible driving forces responsible for the diffusion of Au, Ni, and Cu atoms are discussed in this paper.
Cross-reference maximum likelihood reconstruction for positron emission tomography with empiric studies
(2001-08-01)
Chen, J
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Tu, K
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Chen, T
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Lu, H
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Liu, R