Browsing by Author "Chen, Chen-Yu"

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A Cross-Layer Congestion Avoidance Routing Scheme in Vehicular Ad Hoc Networks
(2014-01-01)
Yang, Chiao-Ling
;
Chung, Yao-Hsing
;
Chen, Chen-Yu
;
Chang, Chung-Ju
;
電機資訊學士班
We propose a cross-layer congestion avoid-ance routing (CCAR) scheme for VANETs based on IEEE 802.11p/WAVE (wireless access in vehicular environment) protocol. Due to highly dynamic network topology, the forwarders are selected one by one. The CCAR scheme first adjust the number of candidates adaptively so that senders have high probability to find a candidate as the forwarder. Then it dynamically adjusts the selection probability of each service channel (SCH) based on traffic load of SCHs to make channel load balanced. Finally, the CCAR scheme takes the number of co-channel senders, the loads of each possible forwarder, and the vehicular moving direction into account to determine the most appropriate route for senders. Simulation results show that the proposed CCAR scheme achieves lower packet delay (higher system uplink through-put) than the conventional GyTAR and AODV schemes by amounts of 95% and 95.7%, (8.4% and 19.2%,) respectively, when the number of vehicles is 150.
Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate
(2014-04-01)
Lin, Yueh-Chin
;
Huang, Mao-Lin
;
Chen, Chen-Yu
;
Chen, Meng-Ku
;
Lin, Hung-Ta
A low interface trap density (D-it) Al2O3/In0.53Ga0.47As/Si MOS capacitor fabricated on an In0.53Ga0.47As heterostructure layer directly grown on a 300 mm on-axis Si(100) substrate by MOCVD with a very thin buffer layer is demonstrated. Compared with the MOS capacitors fabricated on the In0.53Ga0.47As layer grown on the lattice-matched InP substrate, the Al2O3/In0.53Ga0.47As MOS capacitors fabricated on the Si substrate exhibit excellent capacitance-voltage characteristics with a small frequency dispersion of approximately 2.5%/decade and a low interlace trap density D-it close to 5.5 x 10(11)cm(-2) eV(-1). The results indicate the potential of integrating high-mobility InGaAs-based materials on a 300 mm Si wafer for post-CMOS device application in the future. (C) 2014 The Japan Society of Applied Physics