Browsing by Author "Chen, Chi-Shi"

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3D Heterogeneous Integration Structure Based on 40 nm- and 0.18 mu m- Technology Nodes
(2015)
Hu, Yu-Chen
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Lin, Chun-Pin
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Hsieh, Yu-Sheng
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Chang, Nien-Shyang
;
Gallegos, Anthony J.
In this paper, a simple process for high yield CMOS-compatible and heterogeneous integrated chip-to-chip structure without TSV is demonstrated. This scheme provides two chips consisted of the shortest interconnect path by Cu/Sn pillar bump and electroless nickel immersion gold (ENIG) pad bonding. One of the key technologies of 3D integration process is bump plating on the uneven topography. Since passivation layer covers the periphery of the top metal layer, subsequent electroplating process resulted to the increase in height of bump edge which is higher than bump center resulting in concave shape. A new and unique plating solution was developed to solve the issue during the electroplating pillar bump. Basic electrical characteristics including resistance and current leakage were investigated with reliability tests. The stable reliability tests results and excellent electrical performance show that the 3D heterogeneous integration structure is potentially applicable for 3D applications in the future.
A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node
(2015-12-01)
Hu, Yu-Chen
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Lin, Chun-Pin
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Chang, Yao-Jen
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Chang, Nien-Shyang
;
Sheu, Ming-Hwa
A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.
An Advanced 3D/2.5D Integration Packaging Approach Using Double-Self-Assembly Method with Complex Topography, and Micropin-Fin Heat Sink Interposer for Pressure Sensing System
(2016-01-01)
Hu, Yu-Chen
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Lin, Chun-Pin
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Chang, Hsiao-Chun
;
Yang, Yu-Tao
;
Chen, Chi-Shi
To cater complex topography sensors and circuit chips for smart lifestyle applications using Internet of Things (IoT), we develop a novel efficient double-self-assembly packaging approach by 3D/2.5D heterogeneous integration. This technology is able to integrate various kinds of processed chips, especially with uneven surface and bottom topography. With liquid surface tension, complex topography chips can be handled and self-aligned on precise locations. Double-self-assembly approach demonstrates temporary bonding on carrier wafer and self-aligned permanent bonding in a pressure sensing system packaging. The optimized volume of liquid to use on various complex topography shapes and areas are investigated, while Cu/In low temperature metal bonding and self-assembly approach for high I/O density and low bonding resistance are demonstrated. Excellent electrical characteristics and mechanical strength of show the feasibility of the double-self-assembly approach on complex topography surface chips packaging applications.
An Implantable 128-Channel Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable mu-Needle Array and Flexible Interposer
(2017-01-01)
Huang, Po-Tsang
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Huang, Yu-Chieh
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Wu, Shang-Lin
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Hu, Yu-Chen
;
Lu, Ming-Wei
For implanted neural-sensing devices, one of the remaining challenges is to transmit stable power/data (P/D) transmission for high spatiotemporal resolution neural data. This paper presents a miniaturized implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable mu-needle array, a flexible interposer and 4 dies by 2.5D/3D TSV heterogeneous SiP technology. The 4 dies are 2 neural-signal acquisition ICs implemented by 90nm CMOS, 1 neural-signal processor by 40nm CMOS and 1 wireless P/D transmission circuitry by 0.18 mu m CMOS. Thus, the proposed wireless microsystem realizes 128-channel neural-signal sensing within the area of 5mm x 5mm, neural feature extraction and wireless P/D transmission using an on-interposer inductor. The overall average power of the circuits in this microsystem is only 9.85mW.
Generalized MLP/BP-based MIMO DFEs for overcoming ISI and ACI in band-limited channels
(2007)
Hsu, Terng-Ren
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Chen, Chi-Shi
;
Hsu, Terng-Yin
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
in this work, we base on generalized multi-layered perceptron neural networks with backpropagation algorithm (Generalized MLP/BP) to construct multi-input multi-output (MIMO) decision feedback equalizers (DFEs). The proposal is used to recover distorted nonretum-to-zero (NRZ) data in wireline parallel bandlimited channels. From the simulations, we note that the proposed design can recover severe distorted NRZ data as well as suppress intersymbol interference (ISI), adjacent channel interference (ACI) and background noise. The better BER performance as compared to a set of LMS DFEs and an MLPIBP-based MIMO DFE is achieved in the wireline parallel band-limited channels where the data rate is ten times as much as the channel bandwidth.