Browsing by Author "Chen, Chia-I"

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A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
(2010-07-01)
Chen, Chia-I
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In deep submicron era, wire delay is no longer negligible and is becoming a dominant factor of the system performance. To cope with the increasing wire delay, several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures by enabling on-chip multicycle communication. In this article, we present a new performance-driven criticality-aware synthesis framework CriAS targeting regular distributed register architectures. To achieve high system performance, CriAS features a hierarchical binding-then-placement for minimizing the number of performance-critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that CriAS can achieve an average of 14.26% overall performance improvement with no runtime overhead as compared to the previous art.
Architectural Exploration of 3D FPGAs towards a Better Balance between Area and Delay
(2011-01-01)
Chen, Chia-I
;
Lee, Bau-Cheng
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Huang, Juinn-Dar
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The emerging 3D technology, which stacks multiple dies within a single chip and utilizes through-silicon vias (TSVs) as vertical connections, is considered a promising solution for achieving better performance and easy integration. Similarly, a generic 2D FPGA architecture can evolve into a 3D one by extending its signal switching scheme from 2D to 3D by means of TSVs. However, replacing all 2D switch boxes (SBs) by 3D ones with full vertical connectivity is found both area-consuming and resource-squandering. Therefore, it is possible to greatly reduce the footprint with only minor delay increase by properly tailoring the structure and deployment strategy of 3D SB. In this paper, we perform a comprehensive architectural exploration of 3D FPGAs. Various architectural alternatives are proposed and then evaluated thoroughly to pick out the most appropriate ones with a better balance between area and delay. Finally, we recommend several configurations for generic 3D FPGA architectures, which can save up to 52% area with virtually no delay penalty.
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family
(2011)
Chen, Chia-I
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
(2011-04-01)
Huang, Juinn-Dar
;
Chen, Chia-I
;
Lin, Yen-Ting
;
Hsu, Wan-Ling
;
電子工程學系及電子研究所
In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that tip to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.
CriAS: A Performance-Driven Criticality-Aware Synthesis Flow for On-Chip Multicycle Communication Architecture
(2009)
Chen, Chia-I
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In deep submicron era, wire delay is no longer negligible and is dominating the system performance. Several state-of-the-art architectural synthesis flows have been proposed for the distributed register architectures to cope with the increasing wire delay by allowing on-chip multicycle communication. In this paper, we present a new performance-driven criticality-aware synthesis flow CriAS targeting regular distributed register architectures. CriAS features a hierarchical binding strategy and a coarse-grained placer for minimizing the number of critical global data transfers. The key ideas are to take time criticality as the major concern at earlier binding stages before the detailed physical placement information is available, and to preserve the locality of closely related critical components in the later placement phase. The experimental results show that 19% overall performance improvement can be achieved on average as compared to the previous work.
Dynamical sequentially-controlled low-power multiplexer device
(2008-08-21)
Huang, Juinn-Dar
;
Chen, Chia-I
Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency.
Input selection encoding for low power multiplexer tree
(2007)
Chang, Hsiao-En
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Huang, Juinn-Dar
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Chen, Chia-I
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With the advent of portable devices, power consumption becomes one of the most important considerations in VLSI designs. Multiplexer (WX) is a basic component massively used in typical VLSI designs. In this paper, we focus on the minimization of switching activities in a MUX tree composed of 2-to-1 MUXes. The key contribution of this paper is: Given the on probabilities and the selection probabilities of input data signals, the proposed heuristic algorithm can properly encode all input data signals such that the power consumption of the resultant MUX tree is minimized. For a 64-to-1 MUX, the experimental results show that a MUX tree encoded by the proposed algorithm consumes 24% less power than a randomly-encoded tree on average.
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
(2010)
Huang, Juinn-Dar
;
Chen, Chia-I
;
Hsu, Wan-Ling
;
Lin, Yen-Ting
;
Jou, Jing-Yang
In deep-submicron era, wire delay is becoming the bottleneck while pursuing high system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this paper, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). With such delay consideration, synthesis task is inherently more complicated than the one with no inter-island delay concern since uncertain interconnect latency is very likely to make a serious impact on whole system performance. Hence we also develop a performance-driven architectural synthesis framework targeting DRFM-IID, which takes the number of inter-island transfers, transfer criticality and resource utilization into account for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is a common indicator for power consumption of on-chip communication.
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
(2012-02-01)
Huang, Juinn-Dar
;
Chen, Chia-I
;
Hsu, Wan-Ling
;
Lin, Yen-Ting
;
Jou, Jing-Yang
In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.