Browsing by Author "Chen, Chiao-En"

Now showing 1 - 5 of 5

A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems
(2018-01-01)
Chiang, Chih-Hsuan
;
Huang, Shuo-An
;
Chen, Chiao-En
;
Yang, Chia-Hsiang
;
電子工程學系及電子研究所
The generalized geometric mean decomposition (GGMD) is a recently proposed matrix decomposition which can be viewed as a computationally efficient counterpart of the conventional geometric mean decomposition (GMD). As the GMD is the core algorithm in many high performance precoders and equalizers such as the Tomlinson-Harashima precoder and decision feedback equalizer, GGMD facilitates a more computationally efficient implementation while exhibiting identical performance. This work presents the first GGMD processor in the open literature, supporting various matrix sizes by leveraging the reconfigurable processing element (PE) using coordinate rotation digital computers (CORDICs). The implemented GGMD processor supports matrix sizes of 2(n) which ranges from 2 x 2 to 16 x 16, and the throughput performance is maximized through a PE array architecture. The chip integrates 326.9K gates in an area of 1.65 mm(2) in a 90-nm CMOS technology with the maximum throughput achieving 450K matrices/sec for a 16 x 16 matrix at 125 MHz. It dissipates 20.7-28.5 mW at 125 MHz from a 1V supply. Compared to previous GMD designs, this work supports a larger MIMO system with lower hardware complexity and power consumption.
A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems
(2017-02)
Tsai, Yu-Cheng
;
Chen, Chiao-En
;
Yang, Chia-Hsiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a geometric-mean-decomposition (GMD) processor for multiple-input multiple-output (MIMO) communication systems. The proposed GMD pro cessor has a flexible architecture that supports channel matrices of arbitrary dimensions. A complex-valued bi-diagonalization is proposed at the preprocessing stage, which substantially reduces the overall hardware complexity. The proposed GMD processor naturally supports an economic channel state information (CSI) feedback mechanism, rendering it highly suitable for frequency-division- duplexing (FDD) systems. To illustrate the performance of the proposed architecture, we demonstrate an efficient implementation supporting 2 to 8 spatial streams in a 90-nm CMOS technology. The latency constraint of 16 mu s specified in the 802.11ac standard is adopted for this hardware realization. The chip integrates 437.7 K gates in 1.830 x 1.829 mm(2) and dissipates 125.5 mW at 66.67 MHz from a 1 V supply. Compared with the existing GMD implementations, this work supports GMD for matrices of larger dimensions with comparable silicon area, despite the added spatial information feedback capability. Index Terms-CORDIC, geometric mean decomposition
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems
(2018-11-01)
Yeh, Chun-Yu
;
Chu, Ting-Chung
;
Chen, Chiao-En
;
Yang, Chia-Hsiang
;
電子工程學系及電子研究所
Millimeter-wave (mm-Wave) communication, operating from 30- to 300-GHz bands with wider available spectrum, has now emerged as a promising solution for future wireless systems. To reduce the hardware complexity of mm-Wave transceivers, beam-selection techniques combined with beamspace multiple-input multiple-output (MIMO) communications have been proposed in the literature. In such a system, beam selection is performed to exploit the near-sparse nature in the mm-Wave channel and, hence, is crucial to the system performance. This paper presents the world's first digital signal processing (DSP) architecture design for beam selection operation in an mm-Wave multi-user MIMO system. A computationally efficient beam-selection algorithm is first presented. Based on the proposed algorithm, a hardware-scalable beam selection processor is implemented using coordinate rotation digital computers arithmetic. To establish the validity of the concept, the proposed processor is implemented in a 40-nm CMOS technology, integrating 360k logic gates in an area of 0.5625 mm(2), while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users.
A Systolic Array Based GTD Processor With a Parallel Algorithm
(2015-04-01)
Yang, Chia-Hsiang
;
Chou, Chun-Wei
;
Hsu, Chia-Shen
;
Chen, Chiao-En
;
電子工程學系及電子研究所
Generalized triangular decomposition (GTD) has been found to be useful in the field of signal processing, but the feasibility of the related hardware has not yet been established. This paper presents (for the first time) a GTD processor architecture with a parallel algorithm. The proposed parallel GTD algorithm achieves an increase in speed of up to 1.66 times, compared to the speed of its conventional sequential counterpart for an 8x8 matrix. For hardware implementation, the proposed reconfigurable architecture is capable of computing singular value decomposition (SVD), geometric mean decomposition (GMD), and GTD for matrix sizes from 1x1 to 8x8. The proposed GTD processor is composed of 16 processing cores in a heterogeneous systolic array. Computations are distributed over area-efficient coordinate rotation digital computers (CORDICs) to achieve a high throughput. To establish the validity of the concept, a GTD processor was designed and implemented. The latency constraint of 16 mu s specified in the 802.11ac standard is adopted for the hardware realization. The proposed design achieves a maximum throughput of 83.3k matrices/s for an 8x8 matrix at 112.4 MHz. The estimated power and core area are 172.7 mW and 1.96 mm(2), respectively, based on standard 90 nm CMOS technology.
An Iterative Geometric Mean Decomposition Algorithm for MIMO Communications Systems
(2015-01-01)
Chen, Chiao-En
;
Tsai, Yu-Cheng
;
Yang, Chia-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper presents an iterative geometric mean decomposition (IGMD) algorithm for multiple-input-multiple-output (MIMO) wireless communications. In contrast to the conventional geometric mean decomposition (GMD) algorithm, the proposed IGMD does not require the explicit Kth root computation in the preprocessing stage but depends on a carefully constructed iterative procedure that generates the GMD in its limit. We prove analytically that the proposed IGMD is guaranteed to converge to the exact GMD under certain sufficient conditions, and propose three different constructions achieving this condition. Both numerical simulations and complexity analysis of the proposed IGMD have been conducted and compared with the conventional GMD. Simulation results show that our new IGMD algorithm effectively reduces the complexity overhead and hence is more advantageous for low-complexity implementations.