Browsing by Author "Chen, Chien-Fu"

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A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-12-01)
Chiu, Shih-Wen
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Wang, Jen-Huo
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Chang, Kwuang-Han
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Chang, Ting-Hau
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Wang, Chia-Min
Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.
Current Sensorless Control for Dual-Boost Full-Bridge PFC Converter
(2017-01-01)
Chen, Hung-Chi
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Lu, Che-Yu
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Chen, Chien-Fu
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a current sensorless control for dual-boost full-bridge (DBFB) converter with power factor correction (PFC) function. In this topology, the short-through problem can be avoided, and the freewheeling current flows through the independent diode rather than the body diodes of switches. Therefore, the reliability and availability can be improved. The proposed current sensorless control scheme only requires input and output voltages, and that is a simple control strategy without any current sensor. At first, the equivalent single-switch model of the dual-boost full-bridge PFC converter is analyzed and derived. In addition, the experimental control algorithm is implemented by using the DSP TMS320F28335 chip. Finally, some simulation and experimental results are given to validate the performance of the proposed current sensorless control method.
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM
(2013)
Shen, Chang-Hong
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Shieh, Jia-Min
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Wu, Tsung-Ta
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Huang, Wen-Hsien
;
Yang, Chih-Chao
For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.