Browsing by Author "Chen, Chih-Lung"

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A (50,2,4) Nonbinary LDPC Convolutional Code Decoder Chip over GF(256) in 90nm CMOS
(2012)
Lin, Chia-Lung
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電機學院
A memory-based (m(s) = 50, d(v) = 2, d(c) = 4) nonbinary LDPC convolutional code (NB-LDPC-CC) decoder over GF(256) with layered scheduling is presented. The proposed architecture-aware construction features fewer memory banks, low degree, low period, and better performance. To the best of our knowledge, this is the first architecture discussion and implementation for NB-LDPC-CC decoders. We optimized the architecture of message first-in-first-out (M-FIFO), check node unit, and variable node unit in terms of area and throughput. Jointly designing code and architecture, overall normalized area efficiency can be enhanced by more then six times with respect to decoders of nonbinary LDPC block codes (NB-LDPC BCs). After fabricated in 90nm CMOS, our prototype NB-LDPC-CC decoder chip can achieve maximum throughput of 22.8Mbps with frequency of 285MHz. The measured average power is 211mW at a typical operating voltage of 1.0V.
A 0.92mm(2) 23.4mW Fully-Compliant CTC Decoder for WiMAX 802.16e Application
(2009)
Yen, Shao-Wei
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Hu, Ming-Chih
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Jou, Shyh-Jye
An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm(2) can achieve 30Mb/s with 23.4mW power consumption.
A 1-100Mb/s 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Network
(2014)
Chen, Chih-Lung
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Wu, Sheng-Jhan
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1 similar to 100Mb/s with power consumption of 0.5 similar to 9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.
A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder for Small Cell Applications
(2015)
Lee, Xin-Ru
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Yang, Chih-Wen
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.
A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction
(2009)
Chen, Chih-Lung
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Lin, Kao-Shou
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Chang, Hsie-Chia
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Fang, Wai-Chi
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Lee, Chen-Yi
In this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 x 1.4 mm(2). The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.
A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder
(2012-04-01)
Chen, Chih-Lung
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Lin, Yu-Hsiang
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents a (491,3,6) time-varying low-density parity check convolutional code (LDPC-CC) decoder chip. This work combines the algorithm level, node level, and bit level optimizations to achieve over 2 Gb/s throughput with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activation scheduling with concealing channel values, which can not only achieve twice faster decoding convergence speed than log-belief propagation (log-BP) algorithm, but also reduce the 17% message storage capacity. The node level optimization duplicates the check node units and variable node units and unfolds the message storage first-in-first-outs (FIFOs) so that the throughput becomes twelve multiplying with clock frequency. In the meantime, the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has been fabricated in 90 nm CMOS technology with core area of 2.37 x 1.14 mm(2). Maximum throughput 2.37 Gb/s is measured under 1.2 V supply with energy efficiency of 0.024 nJ/bit/proc. Depending on the operation mode, power can be scaled down to 90.2 mW while maintaining 1.58 Gb/s at 0.8 V supply.
A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
(2010-11-01)
Lin, Yi-Min
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Bjorck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.
A 26.9K 314.5Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
(2009)
Lin, Yi-Min
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Borck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.
A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for Solid-State Drive Applications
(2015)
Ho, Kin-Chu
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Chen, Chih-Lung
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Liao, Yen-Chin
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Chang, Hsie-Chia
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Lee, Chen-Yi
As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces.
A 3.66Gb/s 275mW TB-LDPC-CC Decoder Chip for MIMO Broadcasting Communications
(2013)
Chen, Chih-Lung
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Lan, Yu-Cheng
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm(2) area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications
(2012-09-01)
Yen, Shao-Wei
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Hung, Shiang-Yu
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Jou, Shyh-Jye
"An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s mm(2) and energy efficiency of 62.4 pJ/b, respectively."
A 520k (18900,17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
(2016-04)
Ho, Kin-Chu
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Chen, Chih-Lung
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Chang, Hsie-Chia
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Although Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down design methodology, which not only goes through code construction and optimization, but also hardware implementation to meet all the critical requirements, is presented. A two-step array dispersion algorithm is proposed to construct long LDPC codes with a small submatrix size. Then, the constructed LDPC code is optimized by masking matrix to obtain better bit-error rate (BER) performance and lower errorfloor. In addition, our LDPC codes have a diagonal-like structure in the parity-check matrix leading to a proposed hybrid storage architecture, which has the advantages of better area efficiency and large enough data bandwidth for high decoding throughput. To be adopted for NAND flash applications, an (18 900, 17 010) LDPC code with a code-rate of 0.9 and submatrix size of 63 is constructed and the field-programmable gate array simulations show that the error floor is successfully suppressed down to BER of 10(-12). An LDPC decoder using normalized min-sum variable-node-centric sequential scheduling decoding algorithm is implemented in UMC 90-nm CMOS process. The postlayout result shows that the proposed LDPC decoder can achieve a throughput of 1.58 Gb/s at six iterations with a gate count of 520k under a clock frequency of 166.6 MHz. It meets the throughput requirement of both NAND flash memories with Toggle double data rate 1.0 and open NAND flash interface 2.3 NAND interfaces.
A 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communications
(2016-01-01)
Lin, Chia-Lung
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Liu, Rong-Jie
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm(2), drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications
(2015-02-01)
Lee, Xin-Ru
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
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電子工程學系及電子研究所
This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3 K gate count can achieve 7.92 Gb/s data rate and power consumption of 437.2 mW under 1.2 V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.
A low-power Viterbi decoder based on scarce state transition and variable truncation length
(2007)
Lin, Dah-Jia
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Lin, Chien-Ching
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
The ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.
Adjusted Robust Soliton Distribution (ARSD) with Reshaped Ripple Size for LT Codes
(2013)
Yen, Kuo-Kuang
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Liao, Yen-Chin
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Chen, Chih-Lung
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Chang, Hsie-Chia
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電子工程學系及電子研究所
In this work, we improve the performance of robust Soliton distribution (RSD) for LT codes by reshaping its expected ripple size. Our goal is to make the ripple size as close to a constant theta k as possible during BP decoding process, where 0 < theta <= 1 is called ripple size ratio (RSR) and k is the total number of input symbols. We only adjust the proportion of degree 1, degree 2 and the maximum existing degree in RSD to minimize the mean squared error between the expected ripple size and the constant theta k. In addition, we develop upper and lower bounds of RSR as well as an indicator for choosing RSD. Simulation results show that by carefully choosing RSR, the adjusted RSD (ARSD) is able to outperform RSD in terms of successful decoding rate. Compared to RSD, ARSD also reduces the average overhead needed to decode all k input symbols.
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
(2015-03-01)
Lee, Xin-Ru
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Yang, Chih-Wen
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
This brief presents an area-efficient relaxed halfstochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-errorrate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product-algorithm-to-stochastic conversion of VNU, a dynamic random number generation method, which is used for sampling a stochastic symbol, is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in a 90-nm process. According to the results of postlayout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability.
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm
(2016-09)
Lin, Chia-Lung
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Tu, Shu-Wen
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Chen, Chih-Lung
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Chang, Hsie-Chia
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Lee, Chen-Yi
Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24mm(2) and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.
An Improved LT Encoding Scheme with Extended Chain Lengths
(2012-01-01)
Yen, Kuo-Kuang
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Chen, Chih-Lung
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Chang, Hsie-Chia
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交大名義發表
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National Chiao Tung University
The BP decoding terminates frequently during the early stage for LT codes with the robust Soliton distribution. Generally, more than 90% of undecoded input symbols result from decoding termination within the range 0 <= n <= k/2, where n and k are the decoded and total number of input symbols, respectively. This study focuses on reducing the symbol loss probability by preventing early decoding termination. Input symbols can be divided into decoding chains with respect to the connectivity of degree-2 encoding symbols such that neighbors of a degree-2 encoding symbol belong to the same decoding chain. The number of input symbols in a decoding chain is called the chain length. It is found that the average chain length is shorter if the decoding termination occurs within 0 <= n <= k/2. We propose an encoding scheme which increases the chain length to avoid early decoding termination. Each code block is divided into two groups - the first one contains tau randomly selected input symbols, while the rest k - tau symbols form the second group. Neighbors of any degree-2 encoding symbol are restricted from different groups of input symbols. The probability that two degree-2 encoding symbols have a neighbor in common is increased, leading to longer decoding chain on average. Simulation results show that the symbol loss probability of the proposed encoding scheme is always lower than that of the LT encoding. The improvement by our scheme in the symbol loss probability increases with k. In comparison with the LT encoding, when the overhead is sufficiently large, the proposed scheme also achieve higher probability of successful decoding.
An Improved LT Encoding Scheme with Extended Chain Lengths
(2012-01-01)
Yen, Kuo-Kuang
;
Chen, Chih-Lung
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Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The BP decoding terminates frequently during the early stage for LT codes with the robust Soliton distribution. Generally, more than 90% of undecoded input symbols result from decoding termination within the range 0 <= n <= k/2, where n and k are the decoded and total number of input symbols, respectively. This study focuses on reducing the symbol loss probability by preventing early decoding termination. Input symbols can be divided into decoding chains with respect to the connectivity of degree-2 encoding symbols such that neighbors of a degree-2 encoding symbol belong to the same decoding chain. The number of input symbols in a decoding chain is called the chain length. It is found that the average chain length is shorter if the decoding termination occurs within 0 <= n <= k/2. We propose an encoding scheme which increases the chain length to avoid early decoding termination. Each code block is divided into two groups - the first one contains tau randomly selected input symbols, while the rest k - tau symbols form the second group. Neighbors of any degree-2 encoding symbol are restricted from different groups of input symbols. The probability that two degree-2 encoding symbols have a neighbor in common is increased, leading to longer decoding chain on average. Simulation results show that the symbol loss probability of the proposed encoding scheme is always lower than that of the LT encoding. The improvement by our scheme in the symbol loss probability increases with k. In comparison with the LT encoding, when the overhead is sufficiently large, the proposed scheme also achieve higher probability of successful decoding.