Browsing by Author "Chen, Chih-Ning"

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Parallel scrambler for high-speed applications
(2006-07-01)
Lin, Chih-Hsien
;
Chen, Chih-Ning
;
Wang, You-Jiun
;
Hsiao, Ju-Yuan
;
Jou, Shyh-Jye
In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one XOR gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded XOR operation is used as a basic circuit block of the parallel scrambler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-mu m CMOS process.