Browsing by Author "Chen, Chih-Yang"

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A reliability model for low-temperature polycrystalline silicon thin-film transistors
(2007-05-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Lee, Po-Hao
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We proposed here a reliability model that successfully. introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.
Analysis of negative bias temperature instability in body-tied low-temperature polycrystalline silicon thin-film transistors
(2008-02-01)
Chen, Chih-Yang
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.
Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors
(2007)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation. (c) 2007 The Electrochemical Society.
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Tong-Yi
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
Dynamic negative bias temperature instability in p-channel low-temperature poly-Si thin-film transistors was studied in this paper. The degradation of the devices was found to be voltage and temperature dependent. In addition, the frequency and duty ratio of the gate pulse affects the degree of the device degradation. The mechanism of the device degradation was investigated, and a physical model is proposed to explain the mechanism.
Effect of chemical mechanical polish process on low-temperature poly-SiGe thin-film transistors
(2006)
Shieh, Ming-Shan
;
Chen, Chih-Yang
;
Hsu, Yuan-Jiun
;
Wang, Shen-De
;
Lei, Tan-Fu
The improvement of polycrystalline silicon germanium thin-film transistors (poly-SiGe TFTs) using NH(3) passivation and chemical mechanical polishing (CMP) process was examined. Experimental results indicated that NH(3) passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibit: higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio due to the smooth poly-SiGe interface.
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation
(2008-03-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Yang, Tsung-Yu
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I-on/I-min current ratio 1.9 x 10(6) are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO2/polysilicon interface. Significant improvements on subthreshold swing and I-min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage similar to 1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I-on/I-min current ratio 1.21 x 10(7), which is suitable for the application of system-on panel (SOP). (c) 2007 Elsevier Ltd. All rights reserved.
Plasma damage-enhanced negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors
(2006-11-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Chen, Wei-g Chen
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
In this letter, a mechanism that will make negative bias temperature instability (NBTI) be accelerated by plasma damage in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is presented. The experimental results confirm that the mechanism, traditionally found in the thin gate-oxide devices, does exist also in UPS TFTs. That is, when performing the NBTI measurement, the UPS TFTs with a larger antenna ratio will have a higher degree in degradation of the threshold voltage, effective mobility, and drive current under NBTI stress. By extracting the related device parameters, it was demonstrated that the enhancement is mainly attributed to the plasma-damage-modulated creating of interfacial states, grain boundary trap states, and fixed oxide charges. It could be concluded that plasma damage will speed up the NBTI and should be avoided for the UPS TFT circuitry design.
Plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Shen-De
;
Shieh, Ming-Shan
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We have investigated the impact of plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The LTPS TFTs having different antenna structures were used to study the effects of the plasma-etching process. We observed that performance instability occurred for the devices having a relatively large-area antenna. Plasma damage mainly caused nonuniform distribution of the threshold voltages in the LTPS TFTs, presumably because of charge trapping in the gate dielectric during the plasma-etching process. The reliabilities of the LTPS TFTs having larger antenna areas were found to be more degraded under gate-bias stress and hot-carrier stress than those of the samples having smaller antenna areas. Because of their enhanced plasma damage, we speculate that the LTPS TFTs having larger antenna areas possess more trap states in the gate dielectrics. During gate-bias stress or hot-carrier stress, therefore, charges can be injected into the gate dielectric through trap-assisted tunneling, resulting in significant degradation of both the performance and reliability. (c) 2006 The Electrochemical Society.
Process induced instability and reliability issues in low temperature poly-Si thin film transistors
(2006)
Chen, Chih-Yang
;
Wang, Shen-De
;
Shieh, Ming-Shan
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We investigated the impact of plasma process on the devices' performance and reliability degradation of low temperature poly-Si thin film transistors (LTPS TFTs). LTPS TFTs with different antenna areas were used to study the effects of the plasma etching process on the devices. The larger TFT antenna area, the more performance instability occurs. The reliability of LTPS TFTs with large antenna areas was found to be degraded from gate bias stress and hot carrier stress.
Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress
(2008-05-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Wu, Woei-Cherrig
;
Su, Chun-Jung
;
Kao, Kuo-Hsing
In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with HfO2 gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the HfO2 gate dielectric is observed for the PBS and PBTI of the HfO2 LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the HfO2 LTPS-TFT.