Browsing by Author "Chen, Chun-Cheng"

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Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-mu m CMOS Process
(2019-01-01)
Chen, Chun-Cheng
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work studied the latch-up path between two PMOS devices powered by different supply voltages in a 0.18- m CMOS process. In IC field applications, such a non-typical latch up path between two PMOS devices was ever fired to cause unrecoverable failures. Through the silicon test chip, the latch-up path between I/O PMOS and core PMOS was investigated in details. The measurement results from the silicon chip with split test structures can be used to investigate the design rules on anode-to-cathode spacing and guard ring placement to prevent such PMOS-to-PMOS latch-up issue. In chip layout of IC products, the PMOS devices in different power domains shall be carefully checked to prevent the occurrence of such unexpected latch-up path.
Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits
(2019-04-01)
Chen, Chun-Cheng
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new optimization design of an active guard ring has been proposed to improve latch-up immunity of CMOS integrated circuits and been successfully verified in a 0.18-mu m 1.8-/3.3-V CMOS technology. Codesigned with the on-chip electrostatic discharge(ESD) protection devices (gate-ground nMOS and gate-VDD pMOS) equipped at the input-output (I/O) pad, the overshooting/undershooting trigger current during latch-up test can be conducted away through the turned-on channels of the ESD protection MOSFET's to the power rails (V-DD or V-SS). Therefore, the trigger current injecting from the I/O devices (that directly connected to the I/O pad) through the substrate to initiate the latch-up occurrence at the internal circuit blocks can be significantly reduced. Thus, the latch-up immunity of the whole chip can be effectively improved under the same placement distance between the I/O cells and the internal circuit blocks. The new proposed design is a cost-efficient solution to improve latch-up immunity and also to mention good ESD robustness of the I/O cells.
Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18-mu m CMOS Technology
(2019-06-01)
Chen, Chun-Cheng
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On-chip decoupling capacitors often formed by varactor or nMOS have been widely used to shunt the power-line noise in integrated-circuit products. Because the N+ cathode of these capacitors is connected to ground, an unexpected latch-up path between I/O pMOS and n-type decoupling capacitors may be accidentally triggered on. In this paper, the non-typical latchup path between I/O pMOS and n-type decoupling capacitors was investigated in 0.18-mu m 1.8/3.3-V CMOS technology. The measurement results from the silicon chip with split test structures have verified that the n-type decoupling capacitor near the I/O pMOS can cause a high risk of latch-up. Therefore, the layout rules between the decoupling capacitor and I/O devices should be carefully defined to prevent the occurrence of such an unexpected latch-up path.