Browsing by Author "Chen, DF"

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A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering
(2005)
Chung, SS
;
Liu, YR
;
Wu, SJ
;
Lai, CS
;
Liu, YC
In this paper, the difference in degradation mechanism for different substrate engineered CMOS devices has been reported for the first time. These two different substrate engineering includes hybrid substrate engineering, with (100) and (110) orientations, and strained-Si devices. Different mechanisms are responsible for these two different mobility enhancement schemes. For strained-Si devices, it shows that the dominant mechanism for HC(Hot Carrier) and NBT (Negative Bias Temperature) degradations is attributed to the lateral electric field resulting from the mobility enhancement. While for (110)/(100) substrate engineered devices, the dominant mechanism is due to the dangling bond of the surface. In other words, for (I I 0)/(l 00) substrate, the device degradation is weakly dependent on the mobility enhancement while largely dependent on the bond strength. Finally, the difference in temperature dependence of HC and NBT has also been observed for both strained-Si and (110)/(100) substrate devices. Sophisticated measurement techniques, charge pumping (CP) and gated-diode (GD) measurement, have been employed to understand these device mechanisms. These results provide a guideline for the device design and the understanding of related reliabilities in the popular strained-Si and hybrid substrate technology CMOS devices.
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
(2004)
Chung, SS
;
Feng, HJ
;
Hsieh, YS
;
Liu, A
;
Lin, WM
A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Angstrom-16Angstrom range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate detennination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.