Browsing by Author "Chen, DS"

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A low-power 1.2GHz 0.35um CMOS PLL
(2000)
Juang, DC
;
Chen, DS
;
Shyu, JM
;
Wu, CY
;
電子工程學系及電子研究所
In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35um TSMC CMOS technology. The total power consumption is 9.6mW at 1.2-GHz operating frequency with 1.5V supply voltage. The phase noise is -94dBc at 10KHz offset.