Browsing by Author "Chen, Hou-Yu"

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A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
(2011-11-01)
Chen, Hou-Yu
;
Chen, Chun-Chi
;
Hsueh, Fu-Kuo
;
Liu, Jan-Tsai
;
Shy, Shyi-Long
For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
Experimental Analysis of Quasi-Ballistic Transport in Advanced Si nFinFETs Using New Extraction Method
(2018-09-01)
Lin, Ming-Huei
;
Su, Pin
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Chen, Hou-Yu
;
Lu, Jen-Hsiang
;
Chang, Vincent S.
For the first time, the drain-bias dependence of mean free path, predicted by previous Monte Carlo simulations, is experimentally confirmed in Si nFinFETs by using an improved formulation, considering the additional scatterings attributed to source/drain as well as the carrier degeneracy. This letter indicates that, for optimized Si nFinFETs, the carrier velocity and drive current still increase monotonically with decreasing channel length. However, the degradation in mean free path leads to the saturation in ballistic ratio (similar to 60%), resulting in quasi-ballistic transport for devices even with sub-20-nm channel length.
Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal-Oxide-Semiconductor Technology
(2011-04-01)
Chen, Hou-Yu
;
Lin, Chia-Yi
;
Chen, Min-Cheng
;
Huang, Chien-Chao
;
Chien, Chao-Hsin
High-sensitivity polycrystalline silicon (poly-Si) nanowire field-effect transistor (NW FET) pH sensors using top-down and self-aligned fabrication approaches involving the conventional complementary metal-oxide-semiconductor (CMOS) process are reported. For the top-down NW FET, the shrinkage due to reoxidation enables the nanowire width to be scaled to 40 nm without requiring the use of extra lithography equipment, and this improves the electrical uniformity and the performance of the sensors. The surface-ionic coupling operation of this buried-channel field-effect sensor exhibits superior pH sensitivity (threshold voltage shift > 100 mV/pH) as compared to the surface-channel ion-sensitive FET (ISFET). In addition, we report a novel method for fabricating self-aligned, vertical-channel, poly-Si nanowire sensors. The resulting 65-nm self-aligned vertical-channel poly-Si device was found to be feasible for independent-gate bias control, thus enabling its possible integration in very-large-scale integration (VLSI) circuits. Both the abovementioned approaches enable the manufacture of nanowire devices on a large-scale integrated (LSI) circuit using only CMOS manufacturing processes; this provides a high sensitivity, compact and cost-efficient biosensor systems-on-a-chip application. (C) 2011 The Japan Society of Applied Physics
Fabrication of High-Sensitivity Polycrystalline Silicon Nanowire Field-Effect Transistor pH Sensor Using Conventional Complementary Metal-Oxide-Semiconductor Technology (vol 50, 04DL05, 2011)
(2018-05-01)
Chen, Hou-Yu
;
Lin, Chia-Yi
;
Chen, Min-Cheng
;
Huang, Chien-Chao
;
Chien, Chao-Hsin
Nickel Silicide Formation using Pulsed Laser Annealing for nMOSFET Performance Improvement
(2011)
Chen, Hou-Yu
;
Lin, Chia-Yi
;
Chen, Min-Cheng
;
Huang, Chien-Chao
;
Chien, Chao-Hsin
The formation of a uniform, high tensile stress and low silicide/Si interfacial resistance nickel silicide in nMOSFET by introducing pulsed laser annealing (PLA) is reported. This annealing approach facilitated the phase transformation of nickel silicide to Si-rich NiSi(x) compounds using a low-thermal-budget process, improves the silicide/Si interface regularity and avoids familiar (111) NiSi(2) facet formation at a laser energy of 1.5 J cm(-2). By increasing laser energy density up to 2.3 J cm(-2), the device performance and statistics junction leakage distribution were degraded due to the increased sheet resistance of silicide layer and the destroyed silicide/Si interface morphology. When the PLA with a laser energy density of 1.5 J cm(-2) was employed for nickel silicidation on the p-type Schottky diodes, a 0.16 eV hole Schottky barrier height (SBH) increase from 0.52 to 0.68 eV was observed. In addition, the application of PLA for source/drain silicidation of nMOSFETs demonstrated an 8% enhancement in I(on) I(off) characteristic relative to that obtained through the conventional two-step rapid thermal annealing (RTA). This PLA method holds promise as a potential replacement for current nickel silicide annealing approaches toward extremely scaled-down transistors. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3601849] All rights reserved.
The effect of pulsed laser annealing on the nickel silicide formation
(2010-12-01)
Chen, Hou-Yu
;
Lin, Chia-Yi
;
Huang, Chien-Chao
;
Chien, Chao-Hsin
;
電子工程學系及電子研究所
The pulsed laser annealing (PLA) is used to assist nickel silicide transformation for Schottky barrier height reduction and tensile strain enhancement and the effect of different laser power are investigated. In this report, a two-step annealing process which combine the conventional rapid thermal annealing with pulsed laser annealing is proposed to achieve a smooth silicon-rich NiSi(x) interfacial layer on (1 0 0) silicon. With optimized laser energy, a 0.2 eV Schottky barrier height (SBH) modulation is observed from Schottky diode electrical characterization. Furthermore. PLA provides sufficient effective temperature during silicidation which also lead to increased tensile stress of silicide film than the two-step RTA silicide is also investigated. The SBH modulation and tensile stress enhancement benefits of PLA silicidation are considered as an alternative to the conventional rapid thermal annealing for ultra-scaled devices performance enhancement. (C) 2010 Elsevier B.V. All rights reserved.