Browsing by Author "Chen, Hsiu-Chi"

Now showing 1 - 4 of 4

Asymmetry Hybrid Bonding Using Cu/Sn Bonding with Polyimide for 3D Heterogeneous Integration Applications
(2017-01-01)
Huang, Yen-Jun
;
Chen, Hsiu-Chi
;
Yu, Ting-Yang
;
Lai, Bo-Hung
;
Shih, Yu-Chiao
In this work, hybrid bonding platform is successfully developed with solder bonding and photosensitive polyimide (PI) at 250 degrees C. Since solder may be affected by the curing process of polymer owing to its low melting point; an asymmetry hybrid bonding structure is proposed to overcome this issue. Metal and polymer can be well bonded simultaneously with wide integration flexibility through various ratios of polymer to metal. The mechanical strength of bonded structure is substantially improved with the better use of polymer filling in the extra areas between metal lines. The developed hybrid bonding structure shows excellent electrical characteristics and high wafer level uniformity. Furthermore, the bonded samples also show excellent reliability to endure temperature variation and humidity erosion after temperature cycling test and un-bias highly accelerated stress test. With the advantages of dielectric photosensitivity, excellent bonding qualities, high process flexibilities, strong mechanical strength, good electrical pertbrmance and high stability, the hybrid bonding structures have the outstanding potential to be used in future 3D heterogeneous applications.
Development and Investigation of Ultra-Thin Buffer Layers Used in Symmetric Cu/Sn Bonding and Asymmetric Cu/Sn-Cu Bonding for Advanced 3D Integration Applications
(2017-01-01)
Chen, Hsiu-Chi
;
Kho, Yi-Tung
;
Huang, Yen-Jun
;
Hsieh, Yu-Sheng
;
Chang, Yao-Jen
In this work, a particular ultra-thin buffer layer (UBL) with various thickness ranging from 10 nm to 100 nm and different materials including Co, Ni, Pd and Ti is inserted between Cu/Sn to delay the interdiffusion prior to eutectic bonding. The efficacy of the buffer layer and the bonding quality are systematically conferred using microstructure imaging, material analysis, and electrical performance. In addition to symmetric Cu/Sn bonding with UBL, an asymmetric Cu/Sn-Cu bonding which is proposed to relieve the heat enhanced interdiffUsion issues thereby enhancing the reliability performance is demonstrated with the assistance of UBL technology.
Investigation and Optimization of Ultrathin Buffer Layers Used in Cu/Sn Eutectic Bonding
(2018-07-01)
Tang, Ya-Sheng
;
Chen, Hsiu-Chi
;
Kho, Yi-Tung
;
Hsieh, Yu-Sheng
;
Chang, Yao-Jen
Ultrathin buffer layers (UBLs) with varied thickness ranging from 10 to 100 nm and different materials were used in Cu/Sn eutectic bonding. A Cu/Sn film thinner than 2 mu m could fully react and became stiff and rough Cu-Sn intermetallic compound layer, which leads to failure bonding. Four kinds of semiconductor compatible materials including Ti, Pd, Co, and Ni were inserted between Cu/Sn to delay interdiffusion prior to eutectic bonding. In addition to symmetric Cu/Sn bonding with UBL, asymmetric Cu/Sn-Cu bonding scheme with 50-nm Ni UBL was demonstrated. With good mechanical properties, bonding quality, and electrical characteristics, the application of submicrometer Cu/Sn wafer-level bonding by assistance of buffering layer gives a promising and flexible platform for future 3-D integration applications.
The Influence of Device Morphology on Wafer-Level Bonding with Polymer-Coated Layer
(2016-01-01)
Liang, Hao-Wen
;
Chen, Hsiu-Chi
;
Lin, Chien-Hung
;
Lee, Chia-Lin
;
Yang, Shan-Chun
Thetolerance of device morphology in wafer-level bonding through polymer-coated layer was investigated for the application of 3D integration. Several different pillar heights were fabricated on wafers to simulate the case of bonding with real devices on wafers. Overall, the wafer morphology with polymer-coated layer above devices less than 2 mu m can achieve excellent bonding quality. Furthermore, undamaged carrier wafers can be obtained after laser-assisted de-bonding technology, and post clean treatment. Based on bonding results, this research can provide a practical concept on device morphology for polymer-based temporary wafer-level bonding in 3D integration.