Browsing by Author "Chen, Hsiu-Chih"

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Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs
(2018-10-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
;
Chen, Hsiu-Chih
Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs.
DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries
(2019-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Shiao, Yu-Shao Jerry
;
Lin, Chuang-Ju
;
Huang, Guo-Wei
In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f(T)) and maximum oscillation frequencies (f(max)) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f(T) and f(max) are around 25 GHz and 30 GHz, respectively. The high f(T) and f(m)(ax) as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications. (C) 2019 The Japan Society of Applied Physics
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
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Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
Low-Temperature Microwave Annealing Processes for Future IC Fabrication-A Review
(2014-03-01)
Lee, Yao-Jen
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Cho, Ta-Chun
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
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Lu, Yu-Lun
Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C. Next, enhancing the substitutional carbon concentration ([C] sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.
Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs
(2019-01-01)
Hsueh, Fu-Kuo
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Lee, Chun-Ying
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Xue, Cheng-Xin
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Shen, Chang-Hong
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Shieh, Jia-Min
For the first time, below 400 degrees C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I-on/I-off ratio (similar to 10(8)) with low I-off (pFETs<10(-2) nA/mu m). Moreover, the stackability of the GAA MOSFETs and the differential output of dual-mode 10T SRAM readout enable 2x throughput in the CIM circuitry.
Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft
(2018-01-01)
Li, Kai-Shin
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Wei, Yun-Jie
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Chen, Yi-Ju
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Chiu, Wen-Cheng
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Chen, Hsiu-Chih
In this work, we use thermal-ALD to prepare ferroelectric HfZrO2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of I-D. Lower thermal budget process, CO2 far-infrared laser activation and 400 degrees C Ni silicide are employed in the 2-level metal backend integration for maintaining the orthorhombic phase in HZO thin film and minimizing the hysteresis in IV. NC-FinFET inverter has 77% higher voltage gain compared to FinFET-inverter employing HfO2 gate dielectric. NC-FinFET ring oscillator exhibit small speed and power advantages over FinFET oscillator. For the first time, NC-FET cut-off frequency (F-t) frequency is measured, 23.1 GHz or 23% higher than the control FET Ft. NC-FinFET SRAM was observed to exhibit large noise margin.
RF power FinFET transistors with a wide drain-extended fin
(2017-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
;
Huang, Guo-Wei
;
Chen, Hsiu-Chih
Drain-extended FinFET transistors for RF power applications have been fabricated and is presented in this paper. Power FinFETs with a wide drain extension are proposed to reduce the drain resistance. Compared with conventional drain-extended FinFETs, our proposed new devices exhibit lower on-resistances and better high-frequency performances while keeping a similar breakdown voltage. The enhancements of the on-resistance and peak cutoff frequency are 16 and 56%, respectively, under an optimal drain-extension layout. These experimental results suggest that FinFET transistors with a wide drain extension could be used for RF power applications, increasing the possibility of integrating RF power parts into future FinFET system-on-a-chip technologies. (C) 2017 The Japan Society of Applied Physics