Browsing by Author "Chen, Hsuan-Ku"

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A Multi-Bin Constant Throughput CABAC Decoder for HEVC
(2015)
Chen, Hsuan-Ku
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Fang, Chih-Chung
;
Chang, Tian Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate count (810Mbins/sec) when operating at 270MHz.
A QFHD 30-frames/s HEVC Decoder Design
(2016-04)
Chiang, Pai-Tse
;
Ting, Yi-Ching
;
Chen, Hsuan-Ku
;
Jou, Shiau-Yu
;
Chen, I-Wen
The High Efficiency Video Coding (HEVC) standard provides superior compression with large and variable-size coding units and advanced prediction modes, which leads to high buffer costs, memory bandwidth, and irregular computation for ultra high-definition video decoding hardware. Thus, this paper presents an HEVC decoder with a four-stage mixed block size pipeline to reduce the pipeline stage buffer size by approximately 91% compared with the 64x64 block-based pipeline. The high memory bandwidth due to motion compensation problem was solved by 16 x 16 block-based data access, precision-based data access, and a smart buffer to reduce the data bandwidth by 88%. In addition, for irregular computation, a reconfigurable architecture was adopted to unify the variable-size transform. A common intra-prediction module was also designed with a 4x4 block-based bottom-up computation for variable-size intra prediction and modes in a regular manner. Furthermore, the corner position computation for the motion vector predictor was applied to handle variable-size motion compensation. Finally, the implementation with the TSMC 90-nm CMOS process used 467k logic gates and 15.778 kB of on-chip memory and supported 4096x2160