Browsing by Author "Chen, Hsun-Hsiang"

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Balanced Band-Notched UWB Filtering Circular Patch Antenna With Common-Mode Suppression
(2017-01-01)
Lee, Ching-Her
;
Wu, Jhe-Han
;
Hsu, Chung-I G.
;
Chan, Hsiao-Lan
;
Chen, Hsun-Hsiang
This letter presents a balanced band-notched ultrawide-band (UWB) filtering circular patch antenna fed by a microstrip line. The proposed circuit is composed of a lambda/4 slotline-resonator-based balanced band-notched UWB bandpass filter (BPF) and a stub-loaded circular radiating patch. The compact balanced BPF is new in that the slotline resonator is fed judiciously at its open end so that differential-mode fields can be effectively excited in the slotline resonator. Moreover, it can achieve an all-stop-like common-mode rejection because the slotline resonator is incomplete in structure when in common-mode operation. The way the BPF is coupled to the circular radiating patch is novel in that a good impedancematch can be easily obtained with the aid of two tuning open stubs. A pair of spur-lines was implemented in the microstrip feedline near the plane of symmetry to produce a notch band around 5.5 GHz. Measurement shows that the differential-mode operating band with return loss greater than 10 dB covers 2.95-10.75 GHz except for the notch band of 5.01-6.19 GHz. Very good common-mode suppression is observed with the measured common-mode reflection coefficient greater than -1.78 dB in 1-12 GHz.
ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side
(2020-01-01)
Chen, Hung-Wei
;
Chen, Shen-Li
;
Huang, Yu-Ting
;
Chen, Hsun-Hsiang
;
電子工程學系及電子研究所
This paper studies a composite power n-channel lateral-diffused MOSFET device with a super junction (SJ) and parasitic silicon-controlled rectifier structure (nLDMOS-SJ-SCR) in the drain side, which can be used for electrostatic discharge (ESD) and latch-up (LU) reliability enhancements of 60-V power electronics. For ESD and LU protection considerations, the drain side with an SJ structure integrated with p-n-p- and n-p-n-arranged types of nLDMOS-SCR transistors is demonstrated. According to the experimental data, the layout of the SJ structure in the drain side has positive effects on ESD and LU capabilities. The layout type of nLDMOS-SJ with a pillar width W = 9 mu m has the highest secondary breakdown current (I-t2) values; the ESD (LU) improvement was 46.3% (13.3%) compared with the nLDMOS reference sample. Meanwhile, an nLDMOS-SJ with a pillar width W = 27 mu m has the highest figure of merit (FOM) value. By contrast, an embedded p-n-p-(n-p-n-)arranged type SCR structure was added into the drain side once again. Initially, it has a positive (negative) effect on the ESD reliability. Furthermore, the ESD (figure of merit; FOM) improvement was 37.9% (13.72%) of the corresponding nLDMOS-SJ device for nLDMOS-SJ-SCR (p-n-p) with W = 27 mu m. Overall, an nLDMOS-SJ device integrated with the p-n-p-arranged-type SCR in the drain side is a favorable choice for ESD and LU improvements.