Browsing by Author "Chen, Hua-Mao"

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A Dual-Gate InGaZnO4-Based Thin-Film Transistor for High-Sensitivity UV Detection
(2019-08-01)
Chen, Po-Hsun
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Tsao, Yu-Ching
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Chien, Yu-Chieh
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Chiang, Hsiao-Cheng
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Chen, Hua-Mao
UV-sensing devices have received significant recent attention for applications in areas such as human health, fire detection, and optical communication. One key factor for product commercialization is determining the optimal materials that allow for integration of excellent UV-sensing properties with compatibility with industrial fabrication processes. However, current UV sensors often fail to achieve this due to either mismatched materials or a device that must be excessively large in order to produce enough photocurrent for UV detection. The UV-light-sensing properties of an amorphous InGaZnO4 (IGZO) thin-film transistor with a dual-gate structure and relatively small device size (width/length = 50 mu m/10 mu m) that achieves high sensitivity through a threshold-voltage-(V-th)-adjustment method is proposed. Comparing the drain currents under UV exposure to those under darkened conditions indicates that the ratio between the photoinduced and dark current reaches 10(6). Furthermore, the UV sensitivity of the dual-gate transistors can be adjusted by varying the bottom gate voltage, with each pixel of the sensor then being read out separately via scan line pulses. This allows the dual-gate a-IGZO transistor to be used for high-performance UV sensing while being effectively integrated in display applications.
Abnormal Dual Channel Formation Induced by Hydrogen Diffusion From SiNx Interlayer Dielectric in Top Gate a-InGaZnO Transistors
(2017-03-01)
Chen, Guan-Fu
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chen, Hong-Chih
This letter investigates effects of different channel dimensions in top-gate a-InGaZnO4 thin-film transistors with SiNx interlayer dielectric. In narrow channel devices, hydrogen atoms in the SiNx layer diffuse into the entire active layer, inducing a single channel. However, in wider channel devices, the diffusion distance for hydrogen atoms is insufficient to affect the whole channel, instead inducing a double channel. In addition, under hot carrier stress, narrow and wide channels exhibit different degradation behaviors, with simulations showing a strong electrical field at IGZO near the drain terminal of the main channel, which is unaffected by hydrogen.
Abnormal hump in capacitance-voltage measurements induced by ultraviolet light in a-IGZO thin-film transistors
(2017-01-09)
Tsao, Yu-Ching
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Chang, Ting-Chang
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Chen, Hua-Mao
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Chen, Bo-Wei
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Chiang, Hsiao-Cheng
This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software. Published by AIP Publishing.
Abnormal interface state generation under positive bias stress in TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors
(2012-09-24)
Lo, Wen-Hung
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Chang, Ting-Chang
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Tsai, Jyun-Yu
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Dai, Chih-Hao
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Chen, Ching-En
This Letter studies positive bias stress-induced abnormal interface state on TiN/HfO2 p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in V-th shift but without subthreshold slope degradation. However, charge pumping current (I-CP) shows a significant degradation after stress. Accordingly, the impact ionization-induced Nit located HfO2/SiO2 is proposed to demonstrate the ICP degradation. The AC stress with several frequencies is used to evidence the occurrence of impact ionization. Further, the device with additional pre-existing N-it located SiO2/Si has insignificant degradation due to reduction in stress electric field. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4752456]
Abnormal sub-threshold swing degradation under dynamic hot carrier stress in HfO2/TiN n-channel metal-oxide-semiconductor field-effect-transistors
(2013-07-08)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Chen, Ching-En
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Ho, Szu-Han
This work finds abnormal sub-threshold swing (S.S.) degradation under dynamic hot carrier stress (HCS) in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. Results indicate that there is no change in S.S. after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field. Moreover, the impaired stress field causes the interface states to mainly distribute in shallow states. This results in ON state current and transconductance decreases, whereas S.S. degradation is insignificant after dynamic HCS. The proposed model is confirmed by one-side charge pumping measurement and gate-to-drain capacitance at varying frequencies. (C) 2013 AIP Publishing LLC.
Abnormal threshold voltage shift under hot carrier stress in Ti1-xNx/HfO2 p-channel metal-oxide-semiconductor field-effect transistors
(2013-09-28)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Ho, Szu-Han
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Chen, Ching-En
This work investigates the channel hot carrier (CHC) effect in HfO2/Ti1-xNx p-channel metal oxide semiconductor field effect transistors (p-MOSFETs). Generally, the subthreshold swing (S. S.) should increase during CHC stress (CHCS), since interface states will be generated near the drain side under high electric field due to drain voltage (V-d). However, our experimental data indicate that S. S. has no evident change under CHCS, but threshold voltage (V-th) shifts positively. This result can be attributed to hot carrier injected into high-k dielectric near the drain side. Meanwhile, it is surprising that such V-th degradation is not observed in the saturation region during stress. Therefore, drain-induced-barrier-lowering (DIBL) as a result of CHC-induced electron trapping is proposed to explain the different V-th behaviors in the linear and saturation regions. Additionally, the influence of different nitrogen concentrations in HfO2/Ti1-xNx p-MOSFETs on CHCS is also investigated in this work. Since nitrogen diffuses to SiO2/Si interface induced pre-N-it occurring to degrades channel mobility during the annealing process, a device with more nitrogen shows slightly less impact ionization, leading to insignificant charge trapping-induced DIBL behavior. (C) 2013 AIP Publishing LLC.
An Energy-Band Model for Dual-Gate-Voltage Sweeping in Hydrogenated Amorphous Silicon Thin-Film Transistors
(2019-06-01)
Chen, Guan-Fu
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Chen, Hong-Chih
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Chang, Ting-Chang
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Huang, Shin-Ping
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Chen, Hua-Mao
This paper clarifies the correct transmission mechanism, misattributed in the previous research, of a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) device. Complete drain current-gate voltage (I-D-V-G) transfer characteristics including the forward and backward gate sweeps (gate voltage carried out in the OFF-state -> on-state and the ON-state -> OFF-state) are performed, and the physics models of an energy-band schematic are clearly explained. This paper reveals that the I-D-V-G curve stretch-out behavior of the subthreshold region is due to the leakage of the Poole-Frenkel region. At the Poole-Frenkel regions, electrons transfer to the drain terminal, and holes remain in the valance band of the a-Si:H bulk. The remaining holes represent the positive voltage and cause the electron barrier height lowering. This causes an increase in subthreshold current of the subthreshold region. Finally, three experiments are performed to prove the correctness of these models, and the a-Si TFTs device improvement methods will be proposed to enhance the stability and performance of product of the a-Si TFTs.
Analysis of anomalous traps measured by charge pumping technique in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2012-12-03)
Ho, Szu-Han
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Chang, Ting-Chang
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Lu, Ying-shin
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Lo, Wen-Hung
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Chen, Ching-En
This letter investigates anomalous traps measured by charge pumping technique in high voltage in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors. N-V-high level characteristic curves with different duty ratios indicate that the electron discharge time dominates the value of N for extra traps. By fitting ln (N (t(base level) = 2.5 mu s)-N (t(base level)))-Delta t(base level) at different temperatures and computing the equation t = tau(0) exp (alpha(e,SiO2)d(SiO2) + alpha(e,HfO2)d(HfO2,trap)), results show that these extra traps measured by the charge pumping technique at high voltage can be attributed to high-k bulk shallow traps. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4769444]
Anomalous Gate Current Hump after Dynamic Negative Bias Stress and Negative-Bias Temperature-Instability in p-MOSFETs with HfxZr1-xO2 and HfO2/Metal Gate Stacks
(2013)
Ho, Szu-Han
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Chang, Ting-Chang
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Wu, Chi-Wei
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Lo, Wen-Hung
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Chen, Ching-En
In this study, the authors investigated an anomalous gate current hump after dynamic negative bias stress (NBS) and negative-bias temperature-instability (NBTI) in HfxZr1-xO2 and HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. This result is attributed to hole trapping in high-k bulk. Measuring gate current under initial through body floating and source/drain floating conditions indicates that holes flow from source/drain to gate. The fitting of the gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction under initial. Next, fitting the gate current after dynamic NBS and NBTI indicates Frenkel-Poole then tunneling mechanisms, finally returning to the Frenkel-Poole mechanism. These phenomena can be attributed to hole trapping in high-k bulk and the formula Ehigh-k epsilon(high-k) = Q + E-sio2 epsilon(sio2). To further understand the gate current hump, both Zr-undoped and 8 similar to 10% Zr-doped in high-k bulk devices were used for comparisons. These results indicate that initial gate current is also a significant factor in generating the anomalous gate current hump, and all results obey the hump generation condition of J(Tunneling) << J(Frenkel-Poole). (C) 2013 The Electrochemical Society. All rights reserved.
Charge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-field-effect-transistors under hot carrier stress
(2012-04-09)
Lo, Wen-Hung
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Chang, Ting-Chang
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Tsai, Jyun-Yu
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Dai, Chih-Hao
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Chen, Ching-En
This letter studies the channel hot carrier stress (CHCS) behaviors on high dielectric constant insulator and metal gate HfO2/TiN p-channel metal-oxide-semiconductor field effect transistors. It can be found that the degradation is associated with electron trapping, resulting in G(m) decrease and positive Vth shift. However, Vth under saturation region shows an insignificant degradation during stress. To compare that, the CHC-induced electron trapping induced DIBL is proposed to demonstrate the different behavior of Vth between linear and saturation region. The devices with different channel length are used to evidence the trapping-induced DIBL behavior. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3697644]
Charge trapping induced frequency-dependence degradation in n-MOSFETs with high-k/metal gate stacks
(2011-12-30)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Hung, Ya-Chi
This letter investigates the reliability issues of HfO(2)/Ti(1-x)N(x) metal-oxide-semiconductor field effect transistor in terms of static and dynamic stress. The results indicate threshold voltage (V(th)) instability under dynamic stress is more serious than that under static stress, owning to transient charge trapping within high-k dielectric. Capacitance-voltage techniques verified that electron trapping under dynamic stress was located in high-k dielectric near the source/drain (S/D) overlap region, rather than the overall dielectric. Furthermore, the V(th) shift clearly increases with an increase in dynamic stress operation frequency. This phenomenon can be attributed to the fact that electrons injecting to the S/D overlap region have insufficient time to de-trap from high-k dielectric. We further investigated the impact of different Ti(1-x)N(x) composition of metal-gate electrode on charge trapping characteristics, and observed that V(th) shift decreases significantly with an increase in the ratio of nitride. This is because the nitride atoms diffusing from the metal gate fill up oxygen vacancies and reduce the concentration of traps in high-k dielectric. Crown Copyright (C) 2011 Published by Elsevier B.V. All rights reserved.
Competing weak localization and weak antilocalization in amorphous indium-gallium-zinc-oxide thin-film transistors
(2017-01-09)
Wang, Wei-Hsiang
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Lyu, Syue-Ru
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Heredia, Elica
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Liu, Shu-Hao
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Jiang, Pei-Hsun
We have investigated the gate-voltage dependence and the temperature dependence of the magneto-conductivity of amorphous indium-gallium-zinc-oxide thin-film transistors. A weak-localization feature is observed at small magnetic fields on top of an overall negative magnetoconductivity at higher fields. An intriguing controllable competition between weak localization and weak antilocalization is observed by tuning the gate voltage or by varying the temperature. Our findings reflect controllable quantum interference competition in the electron systems in amorphous indium-gallium-zinc-oxide thin-film transistors. Published by AIP Publishing.
Effect of SiO2 Buffer Layer Thickness on Performance and Reliability of Flexible Polycrystalline Silicon TFTs Fabricated on Polyimide
(2016-12-01)
Chen, Bo-Wei
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Chang, Ting-Chang
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Hung, Yu-Ju
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Huang, Shin-Ping
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Chen, Hua-Mao
This letter investigates flexible polycrystalline silicon thin film transistor performance variation due to different buffer layer thicknesses. In flexible electronics, thermal expansion stress during device fabrication is inevitable. A thicker SiO2 buffer demonstrates better endurance to thermal expansion stress from the polyimide substrate during device annealing. However, if the SiO2 buffer thickness is above a critical point, its weak heat dissipation capability causes the optimal ELA crystallization condition to shift. A thermal expansion stress simulation and TEM photos were utilized to verify performance variation. Furthermore, a similar trend was observed in electrical characteristics after negative bias temperature instability.
Effects of Varied Negative Stop Voltages on Current Self-Compliance in Indium Tin Oxide Resistance Random Access Memory
(2015-06-01)
Lin, Chih-Yang
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Chang, Kuan-Chang
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Chang, Ting-Chang
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Tsai, Tsung-Ming
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Pan, Chih-Hung
We have previously investigated the automatic current compliance property for indium tin oxide (ITO) resistance random access memory (RRAM). Traditionally, for the purpose of protecting RRAM, it is necessary to set equipment current compliance during the set and forming processes of RRAM devices. ITO RRAM devices, however, have an intrinsic capability to limit their current. This letter examines this ITO RRAM current compliance in depth by applying a varied stop-voltage measurement method, where different negative stop voltages were adopted to manipulate oxygen ions. Combined with material analysis and conduction current fitting, a model was established.
Gate Insulator Morphology-Dependent Reliability in Organic Thin-Film Transistors
(2016-02)
Chen, Hua-Mao
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Chang, Ting-Chang
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Tai, Ya-Hsiang
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Chiang, Hsiao-Cheng
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Liu, Kuan-Hsien
In this letter, we investigated the gate insulator morphology affecting on the electric characteristic variation for organic thin-film transistors (OTFTs). From the transfer characteristics, there is a result with leakage current when the gate voltage is lower than the threshold voltage, which is due to the gate insulator thickness variation. Furthermore, regardless of whether the OTFT is operated under positive or negative bias stress, the more severe degradation happened in the hump region of transfer characteristics. Because a thinner gate insulator causes a high electric field, more charges are trapped in a gate dielectric stack.
High-k shallow traps observed by charge pumping with varying discharging times
(2013-11-07)
Ho, Szu-Han
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Chang, Ting-Chang
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Lu, Ying-Hsin
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Wang, Bin-Wei
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Lo, Wen-Hung
In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks. N-T-V-high level characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N-T for extra contribution of I-cp traps. N-T is the number of traps, and I-cp is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I-cp traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different TixN1-x metal gate concentrations. Next, N-T-V-high level characteristic curves with different falling times (t(falling time)) and base level times (t(base level)) show that extra contribution of I-cp traps decrease with an increase in t(falling time). By fitting discharge formula for different t(falling time), the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t(falling time). This current cannot be measured by the charge pumping technique. Subsequent measurements of N-T by charge pumping technique at t(base level) reveal a remainder of electrons trapped in high-k bulk shallow traps. (c) 2013 AIP Publishing LLC.
Hole injection-reduced hot carrier degradation in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric
(2013-02-18)
Tsai, Jyun-Yu
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Chang, Ting-Chang
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Lo, Wen-Hung
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Chen, Ching-En
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Ho, Szu-Han
This work finds a significant difference in degradation under hot carrier stress (HCS) due to additional hole injection in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. A comparison performed on degradation of input/output (I/O) and standard performance (SP) devices showed that performance degradation of the I/O device is worse than the SP device under HCS. For the SP device, both channel-electrons and hot holes can inject into gate dielectric, in which hole acts to diminish the stress field. However, I/O device shows only electron injection. The proposed model is confirmed by gate induced drain leakage current and simulation tool. (C) 2013 American Institute of Physics. [http://dx.doi.org/10.1063/1.4791676]
Hot carrier effect on gate-induced drain leakage current in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors
(2011-07-04)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Ho, Szu-Han
This paper investigates the channel hot carrier stress (CHCS) effects on gate-induced drain leakage (GIDL) current in high-k/metal-gate n-type metal-oxide-semiconductor field effect transistors. It was found that the behavior of GIDL current during CHCS is dependent upon the interfacial layer (IL) oxide thickness of high-k/metal-gate stacks. For a thinner IL, the GIDL current gradually decreases during CHCS, a result contrary to that found in a device with thicker IL. Based on the variation of GIDL current at different stress conditions, the trap-assisted band-to-band hole injection model is proposed to explain the different behavior of GIDL current for different IL thicknesses. (C) 2011 American Institute of Physics. [doi:10.1063/1.3608241]
Hot Carrier Effect on Gate-Induced Drain Leakage Current in n-MOSFETs with HfO2/Ti1-xNx Gate Stacks
(2012)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, Ann-Kuo
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Kuo, Yuan-Jui
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Ho, Szu-Han
"This paper investigates the effect of channel hot carrier stress (CHCS) on gate-induced drain leakage (GIDL) current in n-type metal-oxide-semiconductor field effect transistor (n-MOSFETs) with HfO2/Ti1-xNx gate stacks. It was found that the behavior of GIDL current during CHCS has dependence with the interfacial layer (IL) oxide thickness of high-k/metal gate stacks. As IL thickness becomes thinner, the GIDL current has a gradual decrease during CHCS, which is contrary to the result of thick-oxide IL devices. Based on the variation of GIDL current (Delta I-GIDL) in different stress voltage across gate and drain terminals, trap-assisted band to band holes injection model was proposed to explain the different behavior of GIDL current for different IL thickness. Furthermore, we also investigated the impact of different Ti1-xNx composition of metal gate electrode on the Delta I-GIDL after CHCS, and observed that the magnitude of Delta I-GIDL decreases with the increase of nitride ratio. This is due to the fact that nitride atoms diffusing from the metal gate fill up oxygen vacancies, and reduce the concentration of traps in high-k dielectric. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.001206esl] All rights reserved."
Identical Off-state Current Raise Induced by Photo-induced Schottky Barrier Lowering in a-InGaZnO4 Thin Film Transistors
(2016)
Chen, Hua-Mao
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Chang, Ting-Chang
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Liao, Po-Yung
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Chiang, Hsiao-Cheng
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Chen, Ching-En
This work studies the mechanism of identical photoinduced leakage current in a-InGaZnO4 thin film transistors during reverse gate voltage sweep. There is the identical off-state current with the reverse sweep under UV light irradiation, and the photocurrent for UV light exposure region near the source electrode is more significant than that near the drain electrode, which is different from photocurrent mechanism of low temperature polysilicon TFTs. This is because the photo-generated electrons increase the carrier concentration in a-InGaZnO4 bulk, causing the reduced depletion width of the active layer. Therefore, the back channel of active layer is out of gate control.