Browsing by Author "Chen, Huan-Sheng"

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A 11-mW Quadrature Frequency Tripler with Fundamental Cancellation
(2010)
Tsai, Chien-Chung
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Chang, Derric
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Chen, Huan-Sheng
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Kuo, Chien-Nan
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電子工程學系及電子研究所
A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180um technology. The frequency tripler consumes 11.5mW, while the output buffers consumes 43.1mW, all with supply voltage of 1.8V. The fundamental Harmonic Rejection Ratio (HRR(1)) achieves more than 35dB, and the conversion gain achieves -4.2dB at output frequency of 4.5GHz. The entire chip area occupied 1.4x1.1 mm(2).
A CMOS Up-Conversion Mixer with Wide IF Bandwidth for 60-GHz Applications
(2009)
Chen, Min-Chiao
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Chen, Huan-Sheng
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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交大名義發表
In this paper, a direct up-conversion mixer with wide intermediate frequency (IF) bandwidth is designed and fabricated for 60-GHz applications. The up-converted differential signal is transformed to single-ended signal through an on-chip balun. In addition, an injection-locked frequency tripler is integrated for local oscillator signal generation. The measured results shows the maximum conversion gain of -5.6 dB, the input-referred JAB compression point (IP1dB) of -14 dBm, the third-order intercept point (IIP3) of -4 dBm, and 3-dB IF bandwidth of 3.5 GHz. The proposed up-conversion mixer is fabricated using 0.13-mu m standard CMOS technology, and it draws only 2.25 mA from 1.2-V supply.
A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer
(2009-12-01)
Kuo, Chien-Nan
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Chen, Huan-Sheng
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Yan, Tzu-Chao
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of -5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 mu m CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of 1000 x 1050 mu m(2).
An Efficient Framework for Multirequest Route Planning in Urban Environments
(2017-04-01)
Lu, Eric Hsueh-Chan
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Chen, Huan-Sheng
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Tseng, Vincent S.
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資訊工程學系
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Department of Computer Science
In recent years, research on location-based services has received a lot of interest, in both industry and academia, due to a wide range of potential applications. Among them, one of the active topic areas is the constraint-based route planning on a point-of-interest (POI) network. Most of the previous studies on this topic primarily consider the geographic properties of the POIs in planning a route. However, we consider that the reason that a user visits a POI is that it provides some services that the user needs. In particular, in urban environments, a POI may provide various kinds of services. Hence, the user's requests should be considered. In this paper, we address a novel problem, which is called multirequest route planning, and propose a novel framework to efficiently plan a route for serving multiple user-specified requests. The framework consists of two major modules: planning module, in which four approaches with pruning and caching strategies are proposed for planning a preliminary route, and refinementmodule, in which two refinement mechanisms are proposed for further enhancing the quality of the route. To our best knowledge, this is the first work on route planning that considers multiple services provided by a POI and multiple requests specified by a user, simultaneously. Finally, we perform an extensive experimental evaluation based on three real-world POI data sets and deliver excellent performance.
CIRCUIT AND METHOD FOR IMPLEMENTING FREQUENCY TRIPLED I/Q SIGNALS
(2010-05-20)
Kuo, Chien-Nan
;
Chen, Huan-Sheng
A circuit and a method for implementing frequency tripled I/Q signals are proposed, including receiving two input I/Q signals through frequency multipliers so as to generate two frequency multiplied signals and mixing the input I/Q signals and the corresponding frequency multiplied signals through mixers for generating and outputting two I/Q signals with a frequency three times that of the input I/Q signals. The invention eliminates the requirement for high amplitude of the input signals as in the prior art and has lower power consumption and broader bandwidth and can be used as high frequency signal sources in any single chip processes.