Browsing by Author "Chen, Hung-Ming"

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A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
(2015-09-01)
Pan, Po-Cheng
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Chin, Ching-Yu
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Chen, Hung-Ming
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Chen, Tung-Chieh
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Lee, Chin-Chieh
Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper first introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation. And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variable-gain amplifier, a folded-cascode operational amplifier, and a low dropout regulator. The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.
A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function
(2012)
Aroonsantidecha, Suradeth
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Liu, Sean Shih-Ying
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Chin, Ching-Yu
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Chen, Hung-Ming
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電子工程學系及電子研究所
In this paper, we propose a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. Our thermal model is evaluated by the most recent commercial tool and has an average deviation of 6.5% with 242x speed up. Our placer can reach the same quality compared to Capo and APlace2 with 2-3x speed up. Experiments are tested using ISPD 2005 benchmark with up to 2 million gate design. The results are further evaluated using GSRC Bookshelf Evaluator for total HPWL, and using ICEPAK for temperature distribution. To the best of our knowledge, this is the first thermal-aware placer using analytical thermal model and experimented on large scale design. It takes 6.5 hours to complete entire 2005 ISPD benchmark using our thermal aware placer.
A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction
(2011-11-01)
Lin, Chia-Yi
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a generic multi-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping (selectively load/unload) many long scan chain switching activities. Based on the two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. We can further extend the scheme to a generic N dimension test scheme. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed 2-D scheme achieve significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead, around 1% routing overhead, and the power reduction is over 97%.
A Learning-Based Methodology for Routability Prediction in Placement
(2018-01-01)
Chen, Li-Chin
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Huang, Chien-Chia
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Chang, Yao-Lin
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Chen, Hung-Ming
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電子工程學系及電子研究所
The mutability of a circuit is a critical challenge due to the complexity of design rules. Global routing produces a congestion map on a coarse grid and feeds the results to the placer to optimize the design for reducing detailed-route DRC violations. However, there is a growing gap between global routing and the actual violations in detailed routing. This miscorrelation may end up unroutable for back-end detailed routing. In this work, a methodology as well as the framework How based on machine learning technique is proposed to effectively predict detailed routing violations. After extracting appropriate features from placement, fast global routing and detailed routing violations, we use support vector machine techniques to train the prediction model, different from regression framework. We then also develop a prediction model for DRC violation density which can be integrated into placers. Experimental results show that the proposed approach can effectively forecast routability during placement stage.
A Network-Flow Based Algorithm For Power Density Mitigation at Post-Placement Stage
(2013-01-01)
Liu, Sean Shih-Ying
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Luo, Ren-Guo
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a power density mitigation algorithm at post-placement stage. Our proposed framework first identifies cluster of bins with high temperature, then propagates power density away from high temperature region by balancing regional power density. The problem of balancing regional power density is modeled as a supply-demand problem and solution is obtained with minimal displacement of cells. An analytical temperature profiling algorithm is tightly integrated within the framework to constantly update the temperature profile in response to incremental perturbation to placement. Our proposed approach can effectively reduce maximum temperature compared to previous works on temperature mitigation.
A New Methodology for Noise Sensor Placement Based on Association Rule Mining
(2016-01-01)
Hung, Yu-Hsiang
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Fang, Sheng-Hsin
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Chen, Hung-Ming
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Chen, Shen-Min
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Lin, Chang-Tzu
Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized. The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.
A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction
(2010)
Lin, Chia-Yi
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Chen, Hung-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don\'t care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC\'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%.
A selective pattern-compression scheme for power and test-data reduction
(2007)
Lin, Chia-Yi
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supply the test patterns either through the compressed scan chain whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using minimum transition filling method. Due to shorter length of a compressed scan chain, the potential switching activities and the required storage bits can be both reduced. Furthermore, the proposed scheme also supports multiple scan chains. The experimental results demonstrate that, with few hardware overhead, the proposed scheme can achieve significant improvement in shift-in power reduction and large amount of test data volume reduction.
A Stochastic-Based Efficient Critical Area Extractor on Open Access Platform
(2009-01-01)
Chen, Bo-Zhou
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Chen, Hung-Ming
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Huang, Li-Da
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Pan, Po-Cheng
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電子工程學系及電子研究所
Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.
A Stochastic-Based Efficient Critical Area Extractor on Open Access Platform
(2009-01-01)
Chen, Bo-Zhou
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Chen, Hung-Ming
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Huang, Li-Da
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Pan, Po-Cheng
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電子工程學系及電子研究所
Due to inefficient calculation in current critical area analyzer, in this work we present a method of extracting critical area for short faults from the mask layout of an integrated circuit. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more efficient, thus more suitable for the larger layout. The algorithm has been implemented on OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost, and can still maintain the accuracy at the same time.
A Structure-Based Methodology for Analog Layout Generation
(2019-01-01)
Chen, Yu-Hsien
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Chi, Hao-Yu
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Song, Ling-Yen
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
In order to speed up analog design cycles, analog layout automation is a popular research in recent years. However, most previous works assume that the required design constraints are given by users manually. Designers still take a lot of time to fill-in the required design information. Template-based layout generation is another approach to consider the design constraints, but considerable development efforts are required for each new design and each new technology. In this paper, we propose a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users' input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users' intervention and still keeps the post-layout performance within specifications.
A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
(2013-03-01)
Lee, Ren-Jie
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Chen, Hung-Ming
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交大名義發表
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National Chiao Tung University
IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile that combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.
Accurate prediction of enzyme subfamily class using an adaptive fuzzy k-nearest neighbor method
(2007-09-01)
Huang, Wen-Lin
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Chen, Hung-Ming
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Hwang, Shiow-Fen
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Ho, Shinn-Ying
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生物科技學系
Amphiphilic pseudo-amino acid composition (Am-Pse-AAC) with extra sequence-order information is a useful feature for representing enzymes. This study first utilizes the k-nearest neighbor (k-NN) rule to analyze the distribution of enzymes in the Am-Pse-AAC feature space. This analysis indicates the distributions of multiple classes of enzymes are highly overlapped. To cope with the overlap problem, this study proposes an efficient non-parametric classifier for predicting enzyme subfamily class using an adaptive fuzzy r-nearest neighbor (AFK-NN) method, where k and a fuzzy strength parameter m are adaptively specified. The fuzzy membership values of a query sample Q are dynamically determined according to the position of Q and its weighted distances to the k nearest neighbors. Using the same enzymes of the oxidoreductases family for comparisons, the prediction accuracy of AFK-NN is 76.6%, which is better than those of Support Vector Machine (73.6%), the decision tree method C5.0 (75.4%) and the existing covariant-discriminate algorithm (70.6%) using a jackknife test. To evaluate the generalization ability of AFK-NN, the datasets for all six families of entirely sequenced enzymes are established from the newly updated SWISS-PROT and ENZYME database. The accuracy of AFK-NN on the new large-scale dataset of oxidoreductases family is 83.3%, and the mean accuracy of the six families is 92.1 %. (c) 2006 Elsevier Ireland Ltd. All rights reserved.
ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips
(2014-09-01)
Liu, Sean Shih-Ying
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Chang, Chung-Hung
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Chen, Hung-Ming
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Ho, Tsung-Yi
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電子工程學系及電子研究所
The problem of pin-constrained electrowetting-ondielectric (EWOD) biochips becomes a serious issue to realize complex bio-chemical operations. Due to limited number of control pins and routing resources, additional Printed Circuit Board (PCB) routing layers may be required which potentially raises the fabrication cost. Previous state-of-the-art work has tried to develop a framework that uses a network-flow-based method for broadcast electrodeaddressing EWOD biochips. Nevertheless, greedily merging of electrical pins in previous works is at high risk of producing unroutable design. Routability should have higher priority than pin reduction. While previous works dedicated their effort on pin reduction, we have addressed our attention on routability of broadcast addressing. Experimental results demonstrate that taking routability into consideration can even have higher pin reduction. Viewed in this light, we present ACER, a routability driven clustering algorithm followed by escape routing using integer linear programming that effectively solves both pin merging and routing in broadcast addressing framework. Our proposed algorithm does not greedily focus on pin-reduction. Instead, routability is taken into consideration through agglomerative clustering. Compared to previous state-of-the-art, our proposed algorithm can further reduce required control pins by an average of 13% and route the design using 68% less wirelength.
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines
(2019-01-01)
Chi, Hao-Yu
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Lin, Zi-Jun
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Hung, Chia-Hao
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
In order to improve design productivity, proper layout automation tools are desired for analog circuits. Layout migration is one possible approach to generate a new layout for given circuits with different device sizes or different technology, and still keep the original layout topology. However, routing behaviors are often not mentioned in previous works, which requires a complete rerouting that may not follow the original style. Pan [16] first proposed a Constrained Delaunay Triangulation (CDT) based model to keep the routing behavior during layout migration. However, because the device sizes and related distance may be different in the new layout, some reference lines in CDT models may be removed, resulting in some missing nets after migration. In this paper, a novel Cartesian Detection Line (CDL) based model is proposed to preserve the routing behavior in original layouts. Because alternative lines in the modified placement can be easily found to prevent from missing nets, the proposed CDL model greatly improves the routing completeness during layout migration. Several routing refinement techniques are also proposed to solve the routing issues due to block displacement. In our experiments, the routing completeness can be improved to almost 100% with the proposed CDL model, which greatly reduces the design efforts.
Agglomerative-Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree Optimization
(2013-07-01)
Liu, Sean Shih-Ying
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Lo, Wan-Ting
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Lee, Chieh-Jui
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Chen, Hung-Ming
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電子工程學系及電子研究所
In this article, we propose a flip-flop merging algorithm based on agglomerative clustering. Compared to previous state-of-the-art on flip-flop merging, our proposed algorithm outperforms that of Chang et al. [2010] and Wang et al. [2011] in all aspects, including number of flip-flop reductions, increase in signal wirelength, displacement of flip-flops, and execution time. Our proposed algorithm also has minimal disruption to original placement. In comparison with Jiang et al. [2011], Wang et al. [2011], and Chang et al. [2010], our proposed algorithm has the least displacement when relocating merged flip-flops. While previous works on flip-flop merging focus on the number of flip-flop reduction, we further evaluate the power consumption of clock tree after flip-flop merging. To further minimize clock tree wirelength, we propose a framework that determines a preferable location for relocated merged flip-flops for clock tree synthesis (CTS). Experimental results show that our CTS-driven flip-flop merging can reduce clock tree wirelength by an average of 7.82% with minimum clock network power consumption compared to all of the previous works.
Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization
(2012-01-01)
Liu, Sean Shih-Ying
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Lee, Chieh-Jui
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, an optimization methodology using agglomerative-based clustering for number of flip-flop reduction and signal wirelength minimization is proposed. Comparing to previous works on flip-flop reduction, our method can obtain an optimal tradeoff curve between flip-flop number reduction and increase in signal wirelength. Our proposed methodology outperforms [1] and [12] in both reducing number of flip-flops and minimizing increase in signal wirelength. In comparison with [9], our methodology obtains a tradeoff of 15.8% reduction in flip-flop's signal wirelength with 16.9%additional flip-flops. Due to the nature of agglomerative clustering, when relocating flip-flops, our proposed method minimizes total displacement by an average of 5.9%, 8.0%, 181.4% in comparison with [12], [1] and [9] respectively.
An Analytical Placer for Heterogeneous FPGAs via Rough-Placed Packing
(2017-01-01)
Wu, Wan-Ning
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Chen, Chen
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Chin, Ching-Yu
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Wang, Chun-Kai
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Chen, Hung-Ming
Packing and placement are two crucial stages for FPGA realization. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This work presents an analytical placement framework for heterogeneous FPGAs through a rough-placed packing algorithm. In the packing stage, we first perform a fast wirelength-driven placement for the basic logic units. With the physical information from the initial placement, we implement an affinity-based clustering algorithm while taking the control signal constraints into consideration. In the placement stage, a quadratic global placer is implemented with the techniques of handling the heterogeneity, routing congestion estimation and cell inflation. An incremental placer is performed after the global placement for closing the gap between the global placement and legalization, and a detailed placer is adopted to legalize the blocks and reduce the proposed methodologies can effectively improve the placement solutions.
An Approach to Anchoring and Placing High Performance Custom Digital Designs
(2015)
Liu, Shih-Ying
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Chen, Tung-Chieh
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Custom layouts of digital blocks are often used in mixed-signal designs in order to meet the critical performance requirements. Unlike traditional standard-cell based digital placement, custom-cell based digital placement may need additional manual help and intervention to achieve higher performance. The need for manual intervention is primarily due to the inability of modern analytical placers in delivering satisfactory performance on placing designs without pre-placed blocks. While most design flow works in a flat or top-down fashion, custom digital design generally works in a bottom-up fashion that there is no prior knowledge on I/O pin plan since it is changeable by the owners of modules. Without any or very few fixed I/O locations, modern analytical placers tend to produce unsatisfactory results. In this work, we propose a method, mimicking the process of making beds, to guide state-of-the-art analytical placers to deliver better placement results. With the crafted pseudo anchors and nets, total HPWL on Capo10.5 [1], mPL6 [2], NTUplace3 [3] and VDAPlace [4] have improved by 2.92%, 8.69%, 25.26% and 10.72% respectively on a set of industry custom digital designs and improved by 2.19%, 4.34%, 36.09%, and 14.27% respectively on Peko-Suite1 benchmarks.
An Automatic Synthesis Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric Programming
(2014-01-01)
Hsu, Shih-Hsin
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Chen, Wei-Zen
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Zheng, Jui-Pin
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Liu, Sean S. -Y.
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Pan, Po-Cheng
This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the "SPICE accuracy" device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.