Browsing by Author "Chen, JE"

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A behavior-level fault model for the closed-loop operational amplifier
(2000-09-01)
Chang, YJ
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Lee, CL
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Chen, JE
;
Su, CC
;
電子工程學系及電子研究所
In this paper, a simple behavior-level fault model, which is able to represent the faulty behavior of the closed-loop operational amplifier (OP), is presented. The fault model, derived from the macro equivalent circuit of the OP but verified with transistor level simulation, consists of the offset fault and the limited-current fault. It can represent the faulty behavior of the dosed loop OP of all the transistor parametric (soft) faults and many of the catastrophic (hard) faults. Due to its simplicity, the proposed fault model (1) significantly reduces the complexity of fault simulation, and (2) makes closed-form analysis of the faulty behavior of the closed loop OP feasible when the closed loop OP is used as a basic building block of a complicated circuit. Although derived for DC, it can also be applied to AC fault analysis.
A cocktail approach on random access scan toward low power and high efficiency test
(2005)
Lin, SP
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the Random Access Scan (RAS) scheme offers a solution to alleviate the above problems [6]. In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, Test Response Abundant, Constrained Static Compaction, and Bit Propagation Before Test Vector Dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.
A compiled-code parallel pattern logic simulator with inertial delay model
(1999-11-01)
Huang, KC
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Lee, CL
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Chen, JE
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating inertial functions, to execute event-canceling operation of gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it significantly surpasses the conventional time wheel event-driven simulator in terms of simulation speed. In addition, it is also found that a significant percentage (27%) of hazards can be eliminated when the effect of the inertial delay is considered in the simulation.
A fast and sensitive built-in current sensor for IDDQ testing
(1996)
Lu, CW
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Lee, CL
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Chen, JE
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A methodology for fault model development for hierarchical linear systems
(2000)
Huang, YC
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Lee, CL
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Lin, JW
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Chen, JE
;
Su, CC
In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers(OP) is demonstrated and presented. The methodology, at first, presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. an application of the derived models to Monte-Carlo simulation to save computation time is also demonstrated.
A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC
(2004)
Chen, GX
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Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.
A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI
(1998)
Lu, CW
;
Lee, CL
;
Chen, JE
;
Su, CC
;
電子工程學系及電子研究所
In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.
A scan matrix design for low power scan-based test
(2005)
Lin, SP
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For the scan design, the circuit under test (CUT) in the test mode usually has larger switching activity than in the function mode, causing excessive power dissipation. In this paper, we propose a new Scan Matrix (SM) architecture for the scan-based design to achieve low power testing. The scan flip-flops are connected in a matrix style for test and its addressing is controlled by two ring generators during pattern scanning in. Unlike the traditional scan, for which scan-in data need to pass through a long path and many scan flip-flops switch simultaneously, the proposed approach dynamically forms a low-power scan path to reduce test energy and peak power during shift significantly. The architecture is scalable for large designs and has minimal circuit performance penalty. Experimental results show that, for some larger designs, nearly 99% power savings have been achieved.
A testing scheme for crosstalk faults based on the oscillation test signal
(2002)
Wu, MS
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Lee, CL
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Chang, CP
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Chen, JE
;
電子工程學系及電子研究所
A test scheme for the crosstalk fault based on the oscillation signal is proposed. It uses an oscillation signal applied on an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issue during test generation for the crosstalk fault in the conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show the described test generation procedure is effective in generating test patterns for this scheme.
A two-phase fault simulation scheme for sequential circuits
(1998-09-01)
Wu, WC
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A two-phase fault simulation scheme for sequential circuits is proposed. In this fault simulation, the input sequence is divided into two parts. In the first phase, fault free simulation is performed with the first sequence of patterns. In the second phase, fault simulation is performed with the rest of the patterns. Five cases of faults which result from two-phase fault simulation are discussed in detail. Significant speedup in simulation time can be obtained because this fault simulation approach can quickly drop Case 1 faults, which are time-consuming faults and would be considered undetectable in the traditional three-value fault simulation but are actually detected in exact fault simulation. Almost "exact" results can be obtained for detected faults except for a small percentage of over-detected-faults (ODFs) and under-detected-faults (UDFs).
A unified approach to detecting crosstalk faults of interconnects in deep submicron VLSI
(2004)
Li, KSM
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Lee, CL
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Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier.
Adaptive encoding scheme for test volume/time reduction in SoC scan testing
(2005)
Lin, SP
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
application time. In this paper, we propose and demonstrate an Adaptive Encoding scheme to reduce the test volume and test time for SoC scan test. The scheme, instead of handling test data themselves, encodes them in "packets" according to difference hits of two consecutive test patterns. A decoder machine is designed to decode the compressed data and a repeat filling mechanism from the ATE is adopted to eliminate the synchronization problem. It supports variable block size and is flexible in encoding multi-core test patterns; therefore, the proposed method is effective in SoC scan test. Experimental results show that on average the scheme achieves 73% reduction in test data and more than 16 times of speedup in test application time.
An efficient test and diagnosis scheme for the feedback type of analog circuits with minimal added circuits
(2002)
Lin, JW
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Lee, CL
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Chen, JE
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Analysis of application of the IDDQ technique to the deep sub-micron VLSI testing
(2002-02-01)
Lu, CW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1 x 10(7) gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep sub-micron VLSI for the next ten years.
BIST scheme for DAC testing
(2002-07-18)
Chang, SJ
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A low-cost, built-in self-test (BIST) scheme for a digital-to-analogue converter (DAC) is presented. The basic idea is to convert the DAC output voltages corresponding to different input codes into different oscillation frequencies through a voltage controlled oscillator (VCO), and further transfer these frequencies to different digital codes using a counter. According to the input and output codes, performances of a DAC, such as offset error, gain error, differential nonlinearity (DNL), integral nonlinearity (INL), could be effectively detected by simply using digital circuits rather than complex analogue ones. In addition, the annoying DAC output noise could be naturally filtered out by this BIST method.
Factorization of multi-valued logic functions
(1995)
Wang, HM
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Lee, CL
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Chen, JE
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Fault diagnosis for linear analog circuits
(2001)
Lin, JW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators," which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's.
Fault diagnosis for linear analog circuits
(2000)
Lin, JW
;
Lee, CL
;
Su, CC
;
Chen, JE
;
電子工程學系及電子研究所
This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into discrete signal flow graph, then constructs "diagnosing evaluators", which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power the OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as faults in OP's.
Fault diagnosis of odd-even sorting networks
(1997)
Hu, CW
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Lee, CL
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Wu, WC
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Chen, JE
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交大名義發表
This paper investigates detection and location for single faults in odd-even sorting networks. In the work, we have found that three tests are enough to locate single link fault and four tests are sufficient to detect single sorting element fault in an odd-even sorting network. For location tests for sorting element faults, the numbers of tests depend on the type of faults occurring at the sorting element. For most types of sorting element faults, the numbers are less than four specific tests. For the other types of faults, we have prevented the test generation procedure and binary search procedures to generate the tests. The numbers of location tests are less than (n+log(2)n), where n=log(2)N and N is the number of inputs of the sorting network.
Finite state machine synthesis for at-speed oscillation testability
(2005)
Li, KSM
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Lee, CL
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Jiang, T
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Su, CC
;
Chen, JE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.