Browsing by Author "Chen, Jian-Yu"

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Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
(2016-07)
Chen, Yi-Hang
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Chen, Jian-Yu
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Huang, Juinn-Dar
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電機學院
;
電子工程學系及電子研究所
Power dissipation has become a pressing issue of concern in the designs of most electronic system as fabrication processes enter even deeper submicron regions. More specifically, leakage power plays a dominant role in system power dissipation. An emerging circuit design style, the reconfigurable single-electron transistor (SET) array, has been proposed for continuing Moore\'s Law due to its ultra-low leakage power consumption. Recently, several works have been proposed to address the issues related to automated synthesis for the reconfigurable SET array. Nevertheless, all of those existing approaches consider mandatory fabrication constraints of SET array merely in late synthesis stages. In this article, we propose a synthesis algorithm, featuring input-variable ordering and dynamic product term ordering, for area minimization. The fabrication constraints are taken into account at every synthesis stage of proposed flow to guarantee better synthesis outcomes. We also develop a simulated annealing-based postprocess to find a proper phase assignment of each input variable for further area reduction. Experimental results show that our new methodology can achieve up to 29% area reduction as compared to existing state-of-the-art techniques.
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
(2014-01-01)
Chen, Yi-Hang
;
Chen, Jian-Yu
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As fabrication processes exploit even deeper submicron technology, power dissipation has become a crucial issue for most electronic circuit and system designs nowadays. In particular, leakage power is becoming a dominant source of power consumption. Recently, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore\'s Law due to its ultra-low power consumption. Several automated synthesis approaches have been developed for the reconfigurable SET array in the past few years. Nevertheless, all of those existing methods consider fabrication constraints, which are mandatory, merely in late synthesis stages. In this paper, we propose a synthesis algorithm, featuring both variable reordering and product term reordering, for area minimization. In addition, our algorithm takes those mandatory fabrication constraints into account in early stages for better outcomes. Experimental results show that our new method can achieve an area reduction of up to 24% as compared to current state-of-the-art techniques.
Characteristics and Mechanisms of Silicon-Oxide-Based Resistance Random Access Memory
(2013-03-01)
Chang, Kuan-Chang
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Tsai, Tsung-Ming
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Chang, Ting-Chang
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Wu, Hsing-Hua
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Chen, Jung-Hui
Traditionally, a large number of silicon oxide materials are extensively used as various dielectrics for semiconductor industries. In general, silicon oxide cannot be used as resistance random access memory (RRAM) due to its insulating electrical properties. In this letter, we have successfully produced resistive switching and forming-free behaviors by zinc doped into silicon oxide. The current-voltage fitting data show that current transport mechanism is governed by Poole-Frenkel behavior in high-resistance state and Ohm's law in low-resistance state, consisting with filament theory. Additionally, good endurance and retention reliabilities are exhibited in the zinc-doped silicon oxide RRAM.
Charge Quantity Influence on Resistance Switching Characteristic During Forming Process
(2013-04-01)
Chu, Tian-Jian
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Chang, Ting-Chang
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Tsai, Tsung-Ming
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Wu, Hsing-Hua
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Chen, Jung-Hui
In this letter, we presented that the charge quantity is the critical factor for forming process. Forming is a pivotal process in resistance random access memory to activate the resistance switching behavior. However, overforming would lead to device damage. In general, the overshoot current has been considered as a degradation reason during the forming process. In this letter, the quantity of charge through the switching layer has been proven as the key element in the formation of the conduction path. Ultrafast pulse forming can form a discontinuous conduction path to reduce the operation power.
Endurance Improvement Technology With Nitrogen Implanted in the Interface of WSiOx Resistance Switching Device
(2013-07-01)
Syu, Yong-En
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Zhang, Rui
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Chang, Ting-Chang
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Tsai, Tsung-Ming
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Chang, Kuan-Chang
Incorporation of nitrogen as an oxygen-confining layer in the resistance switching reaction region is investigated to improve the reliability of resistance random access memory (RRAM). The switching mechanism can be attributed to the formation and rupture of conduction filaments. A compatible WSiON (around 5 nm) layer is introduced at the interface of tungsten silicon oxide (WSiOx) and TiN electrode to prevent the randomly diffusing oxygen ions surpassing the storage region of the WSiON layer. The double-layer WSiOx/WSiON memory structure would enhance the endurance over 100 times so as to better confirm the WSiOx RRAM application of nonvolatile memory.
Hopping Effect of Hydrogen-Doped Silicon Oxide Insert RRAM by Supercritical CO2 Fluid Treatment
(2013-05-01)
Chang, Kuan-Chang
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Pan, Chih-Hung
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Chang, Ting-Chang
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Tsai, Tsung-Ming
;
Zhang, Rui
In this letter, we introduced hydrogen ions into titanium metal doped into SiO2 thin film as the insulator of resistive random access memory (RRAM) by supercritical carbon dioxide (SCCO)(2) fluid treatment. After treatment, low resistance state split in to two states, we find the insert RRAM, which means it has an operating polarity opposite from normal RRAM. The difference of the insert RRAM is owing to the resistive switching dominated by hydrogen ions, dissociated from OH bond, which was not by oxygen ions as usual. The current conduction mechanism of insert RRAM was hopping conduction due to the metal titanium reduction reaction through SCCO2.
Joint Temporal and Spatial Error Concealment for Multiple Description Video Coding
(2010-12-01)
Tsai, Wen-Jiin
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Chen, Jian-Yu
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資訊工程學系
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Department of Computer Science
Transmission of compressed video signals over error-prone networks exposes the information to losses and errors. To reduce the effects of these losses and errors, this paper presents a joint spatial-temporal estimation method which takes advantages of data correlation in these two domains for better recovery of the lost information. The method is designed for the hybrid multiple description coding which splits video signals along spatial and temporal dimensions. In particular, the proposed method includes fixed and content-adaptive approaches for estimation method selection. The fixed approach selects the estimation method based on description loss cases, while the adaptive approach selects the method according to pixel gradients. The experimental results demonstrate that improved error resilience can be accomplished by the proposed estimation method.
Joint Temporal and Spatial Multiple Description Coding for H.264 Video
(2010)
Chen, Jian-Yu
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Tsai, Wen-Jiin
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資訊工程學系
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Department of Computer Science
Multiple description video coding (MDC) is one of the techniques used to reduce the detrimental effects caused by transmission over error-prone networks. This paper presents a hybrid MDC method which segments the video along spatial and temporal dimensions, and provides efficient estimation methods for missing description reconstruction. The experimental results confirm the improved error resilience capability achieved by the proposed hybrid MDC in lossy networks.
Low Temperature Improvement Method on Zn:SiOx Resistive Random Access Memory Devices
(2013-04-01)
Chang, Kuan-Chang
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Tsai, Tsung-Ming
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Chang, Ting-Chang
;
Wu, Hsing-Hua
;
Chen, Kai-Huang
To improve the resistive switching properties of the resistive random access memory (RRAM), the supercritical carbon dioxide (SCCO2) fluid is used as a low temperature treatment. In this letter, the Zn:SiOx thin films are treated by SCCO2 fluid mixed with pure water. After SCCO2 fluid treatment, the resistive switching qualities of the Zn:SiOx thin films are carried out by XPS, fourier transform infrared spectroscopy, and IV measurement. We believe that the SCCO2-treated Zn:SiOx thin film is a promising material for RRAM applications due to its compatibility with portable flat panel display.
Origin of Hopping Conduction in Graphene-Oxide-Doped Silicon Oxide Resistance Random Access Memory Devices
(2013-05-01)
Chang, Kuan-Chang
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Zhang, Rui
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Chang, Ting-Chang
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Tsai, Tsung-Ming
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Lou, J. C.
In this letter, a double-active-layer (Zr:SiOx/C:SiOx) resistive switching memory device with a high ON/OFF resistance ratio and small working current (0.02 mA), is presented. Through the analysis of Raman and Fourier transform infrared spectroscopy spectra, we find that graphene oxide exists in the C:SiOx layer. It can be observed that Zr:SiOx/C: SiOx structure has superior switching performance and higher stability compared with the single-active-layer (Zr:SiOx) structure, which is attributed to the existence of graphene oxide flakes formed during the sputter process. I-V characteristics under a series of increasing temperature were analyzed to testify the carrier hopping distance variation, which is further verified by our graphene oxide redox reaction model.
Strong-Form Formulated Generalized Displacement Control Method for Large Deformation Analysis
(2017-10-01)
Yang, Judy P.
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Chen, Jian-Yu
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土木工程學系
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Department of Civil Engineering
The traditional analysis of geometric nonlinearity is mostly based on the weak-formulated Galerkin method such as the finite element method. The element nature has limited its application as a result of numerical integration in the governing equation and quality control of deformed mesh. In the middle of 1990s, the meshfree methods have been developed and become one leading research topic in computational mechanics. Especially, the strong form collocation methods require no additional efforts to process numerical integration and impose Dirichlet boundary condition, thereby making the collocation methods computationally efficient. In the incremental-iterative process, how to accurately reflect the change in the slope of the load-deflection curve of the structure and remain numerically stable are of major concerns. Thus, we propose a strong-form formulated generalized displacement control method to analyze geometric nonlinear problems, where the radial basis collocation method is adopted. The numerical examples demonstrate the ability of the proposed method for large deformation analysis.