Browsing by Author "Chen, Jie-Ting"

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Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events
(2018-03-01)
Chen, Jie-Ting
;
Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The RC-based power-rail electrostatic discharge (ESD) clamp with nMOS of large size has been widely utilized to enhance the ESD robustness of CMOS integrated circuits. However, such circuit design that only detects the rising time of ESD pulse may be accidentally triggered in some conditions, such as fast power-ON, hot-plug, and envelope tracking applications. In this paper, a new power-rail ESD clamp circuit with transient and voltage detection function has been proposed and implemented in a 0.18-mu m 1.8-V CMOS technology. The measurement results from the silicon chip have demonstrated that the new proposed power-rail ESD clamp circuit with adjustable minimum starting voltage (V-starting) can achieve good ESD robustness and avoid triggering under fast power-ON condition. In addition, the proposed circuit has a low standby leakage current of 270 nA at 125 degrees C under normal power-ON condition.
ESD Protection Design for High-Speed Applications in CMOS Technology
(2016-01-01)
Chen, Jie-Ting
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Lin, Chun-Yu
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Chang, Rong-Kun
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Ker, Ming-Dou
;
Tzeng, Tzu-Chien
To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded silicon-controlled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.
ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains
(2019-06-01)
Chen, Jie-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To effectively protect the interface circuit between separated power domains from electrostatic discharge (ESD) damage, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18-mu m 1.8-V/3.3-V CMOS process. Since the DTQSCR embeds four silicon-controlled rectifier paths and a structure of back-to-back diodes, the silicon area can be efficiently reduced more than 30% as compared to the traditional ESD protection design under the same ESD specification. From the measurement results in silicon chip, an interface circuit (level shifter) with the proposed ESD protection design can successfully sustain a human-body-model of greater than 5.5 kV. The proposed ESD protection device is suitable to protect the interface circuits between different power domains.
On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
(2017-10-01)
Chen, Jie-Ting
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.
On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process
(2018-12-01)
Chen, Jie-Ting
;
Lin, Chun-Yu
;
Chang, Rong-Kun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.
RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
(2020-07-01)
Wu, Wei-Min
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Ker, Ming-Dou
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Chen, Shih-Hung
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Chen, Jie-Ting
;
Linten, Dimitri
In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.