Browsing by Author "Chen, Jim-Shone"

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Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
;
Chang, Ting-Chang
;
Chen, Shih-Ching
;
Hsieh, Tien-Yu
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress
(2011-03-01)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide-nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.
Unusual Threshold Voltage Shift Caused by Self-Heating-Induced Charge Trapping Effect
(2010)
Jian, Fu-Yen
;
Chang, Ting-Chang
;
Chu, An-Kuo
;
Chen, Te-Chih
;
Chen, Shih-Ching
This article investigates the threshold voltage (V(t)) shift induced by a self-heating effect for n-channel low temperature poly-Si thin film transistors (TFTs) and finds that there is a shift of more than 3 V in the negative direction after a self-heating operation of 100 ms. The negative V(t) shift can be attributed to the charge-trapping effect caused by the holes generated by trap-assisted band-to-band thermionic field emission and trapped in the grain boundary of the poly-Si film substrate. We used lateral body contact structure to verify that this unusual V(t) shift is related to the holes trapped in the substrate. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3290686] All rights reserved.