Browsing by Author "Chen, Juinn-Ting"

Now showing 1 - 5 of 5

A 0.5V 4.85Mbps Dual-Mode Baseband Transceiver with Extended Frequency Calibration for Biotelemetry Applications
(2008)
Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Huang, Shang-Bin
;
Chen, Tsan-Wen
;
Chen, Juinn-Ting
This work provides a dual-mode transceiver chipset for wireless body area network (WBAN). The modulation schemes include both MT-CDMA and OFDM. A phase-frequency tunable clock generator (PFTCG) is designed with frequency and phase tuning capability on the fly. A rotator-and-synthesizer driven (RSD) frequency pre-calibration with the aid of the PFTCG enables calibration for extended 100ppm frequency error (2.5x of state-of-the-art systems). This chip is manufactured in 90nm standard CMOS process. The supply voltage to the chip core is globally applied at 0.5V with 12 power- and voltage-domain partitions for sleep-active and voltage-scaling management. The PFTCG is operated at 5MHz with RMS jitter 145ps. The transceiver chipset provides maximum 4.85Mbps data rate with 73.7% power reduction in baseband circuit processing.
A dynamic phase-frequency recovery for power reduction in OFDM systems
(2007)
Yang, Mei-Hui
;
Yu, Jui-Yuan
;
Chen, Juinn-Ting
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
A dynamic phase and frequency recovery (DPR & DFR) is proposed for power reduction and performance improvement. By the DPR, signal sampling rate is reduced from Nyquist rate (or higher) to the symbol rate, resulting in reduced ADC circuit power. By the DFR, data is recovered from less-interfered signals. In the MB-OFDM UWB system, the simulations show that the system improves 2.3 dB SNR and reduce 43.75% ADC power consumption with the proposed techniques.
Absolute time delay generating device
(2010-01-21)
Lee, Chen-Yi
;
Yu, Jui-Yuan
;
Yu, Chien-Ying
;
Chen, Juinn-Ting
An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems
(2007)
Yu, Jui-Yuan
;
Chen, Juinn-Ting
;
Yang, Mei-Hui
;
Chung, Ching-Che
;
Lee, Chen-Yi
An all-digital clock generator is designed to enable the clock phase and frequency tuning dynamically during the wireless communications system is in operation. This phase-frequency tunable clock generator (PFTCG) provides 8 clock phases for selection and enables the ADC circuits sampling signals with lower frequency and better sampling phase, resulting in lower power consumption. The PFTCG provides the frequency tuning range +/- 150ppm centered at 5MHz, resulting in high performance due to smaller sampling clock offset. This PFTCG is simulated under the wireless body area network system, and shows a 6.3dB SNR improvement at BER=1 e(-3), and the. hardware is simulated with power 77.56 mu M in the standard process 90nm CMOS technology.
DIGITAL DELAY LINE AND APPLICATION THEREOF
(2010-01-21)
LEE, Chen-Yi
;
Yu, Jui-Yuan
;
Chen, Juinn-Ting
A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.