Browsing by Author "Chen, Jung-Sheng"

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Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process
(2006)
Chen, Jung-Sheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The effect of gate-oxide reliability on MOS switch in the bootstrapped circuit is investigated with the sample-and-hold amplifier in a 130-nm CMOS process. After overstress on the MOS switch of sample-and-hold amplifier, the circuit performances in the frequency domain are measured to verify the impact of gate-oxide reliability on circuit performance.
Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process
(2008-03-01)
Chen, Jung-Sheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device degrades the circuit performance of bootstrapped switch technique.
Fabrication of a miniature CMOS-based optical biosensor
(2007-06-15)
Ho, Wei-Jen
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Chen, Jung-Sheng
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Ker, Ming-Dou
;
Wu, Tung-Kung
;
Wu, Chung-Yu
This work presents a novel, miniature optical biosensor by immobilizing horseradish peroxidase (HRP) or the HRP/glucose oxidase (GOx) coupled enzyme pair on a CMOS photosensing chip with a detection area of 0.5 mm x 0.5 mm. A highly transparent TEOS/PDMS Ormosil is used to encapsulate and immobilize enzymes on the surface of the photosensor. Interestingly, HRP-catalyzed luminol luminescence can be detected in real time on optical H2O2 and glucose biosensors. The minimum reaction volume of the developed optical biosensors is 10 RL. Both optical H2O2 and glucose biosensors have an optimal operation temperature and pH of 20-25 degrees C and pH 8.4, respectively. The linear dynamic range of optical H2O2 and glucose biosensors is 0.05-20 mM H2O2 and 0.5-20 mM glucose, respectively. The miniature optical glucose biosensor also exhibits good reproducibility with a relative standard deviation of 4.3%. Additionally, ascorbic acid and uric acid, two major interfering substances in the serum during electrochemical analysis, cause only slight interference with the fabricated optical glucose biosensor. In conclusion, the CMOS-photodiode-based optical biosensors proposed herein have many advantages, such as a short detection time, a small sample volume requirement, high reproducibility and wide dynamic range. (c) 2007 Published by Elsevier B.V.
Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes
(2006)
Chen, Jung-Sheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the nonstacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under DC stress and AC stress with DC offset, respectively. The small-signal parameters of amplifier with non-stacked structure strongly degrade under such overstress conditions. The gate-oxide reliability in analog circuit can be improved by stacked structure for small-signal input and output applications.
Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
(2009-08-01)
Chen, Jung-Sheng
;
Ker, Ming-Dou
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.
Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology
(2007)
Chen, Jung-Sheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.
Impact of MOSFET gate-oxide reliability on CMOS operational amplifier in a 130-nm low-voltage process
(2008-06-01)
Ker, Ming-Dou
;
Chen, Jung-Sheng
;
電機學院
;
電子工程學系及電子研究所
;
College of Electrical and Computer Engineering
The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the de stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. The impact of soft and hard gate-oxide breakdowns on operational amplifiers with two-stage and folded-cascode structures has been analyzed and discussed. The hard breakdown has more serious impact on the operational amplifier.
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation
(2006-08-01)
Ker, Ming-Dou
;
Chen, Jung-Sheng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new sub-I-V curvature-compensated CMOS bandgap reference, which utilizes the temperature-dependent currents generated from the parasitic n-p-n and p-n-p bipolar junction transistor devices in the CMOS process, is presented. The new proposed sub-l-V curvature-compensated CMOS bandgap reference has been successfully verified in a standard 0.25-mu m CMOS process. The experimental results have confirmed that, with the minimum supply voltage of 0.9 V, the output reference voltage at 536 mV has a temperature coefficient of 19.5 ppm/degrees C from 0 degrees C to 100 degrees C. With a 0.9-V supply voltage, the measured power noise rejection ratio is -25.5 dB at 10 kHz.
New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process
(2007-09-01)
Chen, Jung-Sheng
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-mu m LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with thresh old-voltage compensation enables the analog circuits to be integrated and implemented by the UPS process on glass substrate for an active matrix LCD panel.
Swimming Pool Associated Vittaforma-Like Microsporidia Linked to Microsporidial Keratoconjunctivitis Outbreak, Taiwan
(2019-11-01)
Chen, Jung-Sheng
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Hsu, Tsui-Kang
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Hsu, Bing-Mu
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Chao, Shih-Chun
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Huang, Tung-Yi
We analyzed 2 batches of environmental samples after a microsporidial keratoconjunctivitis outbreak in Taiwan. Results indicated a transmission route from a parking lot to a foot washing pool to a swimming pool and suggested that accumulation of mud in the foot washing pool during the rainy season might be a risk factor.
The impact of gate-oxide breakdown on common-source-amplifiers with diode-connected active load in low-voltage CMOS processes
(2007-11-01)
Chen, Jung-Sheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the nonstacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test. conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output dc voltage levels, are measured to verify the impact of gate-oxide reliability on circuit performances of the common-source amplifiers with diode-connected active load. The small-signal parameters of the common-source amplifier with the nonstacked diode-connected active-load structure are strongly degraded than that with the stacked diode-connected active-load structure due to a gate-oxide breakdown under analog and digital applications. The common-source amplifiers with diode-connected active load are not functionally operational under digital application due to the gate-oxide breakdown. The impact of soft and hard gate-oxide breakdowns on the common-source amplifiers with nonstacked and stacked diode-connected active-load structures has been analyzed and discussed. The hard breakdown has more serious impact on the common-source amplifiers with diode-connected active load.