Browsing by Author "Chen, Jwu-E"

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A multilayer data copy test data com pression scheme for reducing shifting-in power for multiple scan design
(2007-07-01)
Lin, Shih-Ping
;
Lee, Chung-Len
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Chen, Jwu-E
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Chen, Ji-Jan
;
Luo, Kun-Lun
The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works Were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes,a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.
Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits
(2013-12-01)
Huang, Chien-Chih
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Wey, Chin-Long
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Chen, Jwu-E
;
Luo, Pei-Wen
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電機工程學系
Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays
(2017-01)
Huang, Chien-Chih
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Chen, Jwu-E
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Wey, Chin-Long
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電機工程學系
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Department of Electrical and Computer Engineering
Capacitor matching influences linearity performance, which is a critical measure of analog-to-digital converters (ADCs). Various placement techniques have been proposed to eliminate both systematic and random mismatches of capacitor pairs. However, a placement technique that eliminates capacitor mismatches may not result in good linearity performance for successive-approximation-register ADCs because their linearity performance is related to the accuracy of their binary-weighted continued ratio. This paper addresses the critical problem of placement estimation based on ratio mismatch M, overall correlation coefficient L, and performance metrics. A low M and a high L value do not imply higher linearity performance. Therefore, we propose a partition-centering-based symmetry placement algorithm for the layout considering parasitic capacitance matching. The experimental results show that the proposed placement approach can achieve higher linearity performance and a shorter placement generation time compared with the conventional approach.
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
(2015-11)
Huang, Chien-Chih
;
Wey, Chin-Long
;
Chen, Jwu-E
;
Luo, Pei-Wen
;
電子工程學系及電子研究所
The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratiomismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.