Browsing by Author "Chen, K. -M."

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A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si With High Etching Selectivity and Isotropy
(2020-03-01)
Huang, Y. -A.
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Liang, C. -Y.
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Peng, K. -P.
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Chen, K. -M.
;
Huang, G. -W.
A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped n(+) poly-Si deposition followed by a subsequentshallow implantation of BF2+. Both high etching isotropy in n(+) poly-Si and high etching selectivity between n(+) poly-Si and B-doped poly-Si in a Cl-2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of 0.15 mu m . The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications.
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatment
(2018-01-01)
Yeh, M. -S.
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Luo, G. -L.
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Hou, F. -J.
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Sung, P. -J.
;
Wang, C. -J.
Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O-3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the I-ON/I-OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low V-D = 0.6 V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.