Browsing by Author "Chen, K. N."

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BCB-to-oxide bonding technology for 3D integration
(2012-02-01)
Lin, S. L.
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Huang, W. C.
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Ko, C. T.
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Chen, K. N.
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電子工程學系及電子研究所
Process optimization of BCB polymer to silicon oxide bonding was investigated. The suitable bonding temperature is about 300 degrees C, while bond failure of BCB-to-oxide bonding is observed starting from 400 degrees C. Bonding interface morphologies and bond strengths of BCB-to-oxide bonding were investigated as well. PECVD oxide to BCB bonding has better bonding quality than that of thermal oxide to BCB bonding. Si-O-Si bonds may be the reason of a strong BCB to oxide bonding. Water molecules link BCB and oxide surfaces during the initial contact, while Si-O-Si bonds are formed during bonding. This proposed mechanism of BCB-to-oxide bonding provides a guideline for polymer to oxide hybrid bonding technology in 3D integration. (C) 2011 Elsevier Ltd. All rights reserved.
Bonding Temperature Optimization and Property Evolution of SU-8 Material in Metal/Adhesive Hybrid Wafer Bonding
(2011-08-01)
Chen, K. N.
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Cheng, C. A.
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Huang, W. C.
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Ko, C. T.
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電子工程學系及電子研究所
Bonding temperature optimization of SU-8 material for metal/adhesive hybrid bonding was investigated. The good bond quality of SU-8 adhesive can be achieved with the bonding temperature between 150 degrees C and 250 degrees C, while bond failures of SU-8 wafers are observed starting from 275 degrees C. IR transmittance spectra measurements indicate the crosslinks inside SU-8 break and further bond failure is observed due to the large decomposition of epoxy rings and phenyl in plane bending above 275 degrees C. This research provides guidelines of material selection and bonding parameters for heterogeneous integration, 3DIC and MEMS applications using metal/adhesive hybrid bonding.
Controlled large strain of Ni silicide/Si/Ni silicide nanowire heterostructures and their electron transport properties
(2010-11-15)
Wu, W. W.
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Lu, K. C.
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Chen, K. N.
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Yeh, P. H.
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Wang, C. W.
Unusually large and compressively strained Si in nanoheterostructures of Ni silicide/Si/Ni silicide, in which the strain of the Si region can be achieved up to 10%, has been produced with point contact reactions between Si and Ni nanowires in an ultrahigh vacuum transmission electron microscope. The growth rate and relationships between the strain and the spacing of the Si region have been measured. Based on the rate and relationships, we can control the Si dimension and, in turn, the strain of remaining Si can be tuned with appropriate spacing. Since one-dimensional nanoheterostructures may have potential applications in nanoelectronic devices, the existent strain will further affect carrier mobility and piezoresistance coefficients in the Si region. Electrical measurements on the nanodevices from such nanoheterostructures show that the current output closely correlates with the Si channel length and compressive strain. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3515421]
Diffusion of Co-Sputtered Metals as Bonding Materials for 3D Interconnects During Thermal Treatments
(2012-03-01)
Hsu, S. Y.
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Chen, H. Y.
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Chen, K. N.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Diffusion behaviors of co-sputtered metals during thermal treatments were investigated, where these co-sputtered metals can be used as bonding materials for 3D Interconnects. In this paper, we report the diffusion behaviors and discuss the diffusion mechanisms of co-sputtered metals before and after annealing. Atom and vacancy volume, vacancy formation energy, and activation energy are proposed to explain the diffusion direction and diffusion rate among different co-sputtered metals. Based on the excellent bonding performance of this method, Cu/metal co-sputtering bonding is considered as a potential candidate for advanced bonding technology.
Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D Interconnects
(2012)
Chen, K. N.
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Chang, Y. J.
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Ko, C. T.
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Hsu, S. Y.
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Chen, H. Y.
Electrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional Integration
(2011-06-01)
Chen, K. N.
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Young, A. M.
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Lee, S. H.
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Lu, J. -Q.
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電子工程學系及電子研究所
The integrity of bonded Cu interconnects in wafer-level three-dimensional integration has been investigated as the function of pattern size and density, as well as bonding process parameter. The desired pattern density coupled with the application of bonding process profile we developed gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and contact resistance through the entire wafer. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology.
Enhanced growth of low-resistivity titanium silicides on epitaxial Si(0.7)Ge(0.3) on (001)Si with a sacrificial amorphous Si interlayer
(2010-10-01)
Wu, W. W.
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Wang, C. W.
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Chen, K. N.
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Cheng, S. L.
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Lee, S. W.
Enhanced growth of low-resistivity self-aligned titanium silicides on epitaxial Si(0.7)Ge(0.3) with a sacrificial amorphous Si (a-Si) interlayer has been achieved. The a-Si layer with appropriate thickness was found to prevent Ge segregation, decrease the growth temperature, as well as maintain the interface flatness and morphological stability in forming low-resistivity C54-TiSi(2) on Si(0.7)Ge(0.3) grown by molecular beam epitaxy. The process promises to be applicable to the fabrication of high-speed Si-Ge devices. (C) 2010 Published by Elsevier B.V.
Enhanced growth of low-resistivity titanium silicides on epitaxial Si0.7Ge0.3 on (001)Si with a sacrificial amorphous Si interlayer
(2010-10-01)
Wu, W. W.
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Wang, C. W.
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Chen, K. N.
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Cheng, S. L.
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Lee, S. W.
Enhanced growth of low-resistivity self-aligned titanium silicides on epitaxial Si0.7Ge0.3 with a sacrificial amorphous Si (a-Si) interlayer has been achieved. The a-Si layer with appropriate thickness was found to prevent Ge segregation, decrease the growth temperature, as well as maintain the interface flatness and morphological stability in forming low-resistivity C54-TiSi2 on Si0.7Ge0.3 grown by molecular beam epitaxy. The process promises to be applicable to the fabrication of high-speed Si-Ge devices. (C) 2010 Published by Elsevier B.V.
Fabrication of Nano-Scale Cu Bond Pads with Seal Design in 3D Integration Applications
(2011-04-01)
Chen, K. N.
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Tsang, C. K.
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Wu, W. W.
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Lee, S. H.
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Lu, J. Q.
A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO(2) CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.
Integration schemes and enabling technologies for three-dimensional integrated circuits
(2011-05-01)
Chen, K. N.
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Tan, C. S.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Various integration schemes and key enabling technologies for wafer-level three-dimensional integrated circuits (3D IC) are reviewed and discussed. Stacking orientations (face up or face down), methods of wafer bonding (metallic, dielectric or hybrid), formation of through-silicon via (TSV) (via first, via middle or via last) and singulation level (wafer-to-wafer or chip-to-wafer) are options for 3D IC integration schemes. Key enabling technologies, such as alignment, Cu-Cu bonding and TSV fabrication, are described as well. Improved performance, such as lower latency and higher bandwidth, lower power consumption, smaller form factor, lower cost and heterogeneous integration of disparate functionalities, are made possible in the next generation of electronics products with the realisation of 3D IC.
Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes
(2010-12-01)
Chen, K. N.
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Zhu, Y.
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Wu, W. W.
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Reif, R.
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材料科學與工程學系
This paper investigates and reviews the effects of wafer bow in three- dimensional (3D) integration bonding schemes, including copper wafer bonding and oxide fusion wafer bonding with silicon on insulator (SOI)-based layer transfer technology. Wafer bow criteria for good bonding quality and fabrication techniques to minimize wafer bow are introduced for 3D integration technology and applications.
Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding
(2010)
Chen, K. N.
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Shaw, T. M.
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Cabral, C., Jr.
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Zuo, G.
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電子工程學系及電子研究所
We demonstrate a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding. Hybrid Cu-oxide hybrid bonding shows excellent bond quality and performances in terms of alignment, bond strength, and ambient permeation oxidation. Excellent performances of initial reliability and quality evaluations for Cu-oxide hybrid bonding are key milestones in proving manufacturability of 3D integration technology.
Structural Design, Process, and Reliability of a Wafer-Level 3D Integration Scheme with Cu TSVs Based on Micro-bump/Adhesive Hybrid Wafer Bonding
(2012)
Ko, C. T.
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Hsiao, Z. C.
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Chang, Y. J.
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Chen, P. S.
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Huang, J. H.
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5 mu m TSV, 10 mu m microbump, 20 mu m pitch, 40 mu m thin wafer, and 250 degrees C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.
Wafer-Level Self-Aligned Nano Tubular Structures and Templates for Device Applications
(2010-12-01)
Chen, K. N.
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Arnold, J. C.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A method to fabricate self-aligned nano-scale tubular structures is introduced and investigated. These tubular structures, can be fabricated on wafer-level using common CMOS technologies, are robust and cannot be removed through standard etching or resist strip techniques. This method has shown the potential to be used in different nano device applications since the size of nano-scale tubular structures is adjustable. In addition, these structures can be fabricated as nano-scale templates in advanced device applications.