Browsing by Author "Chen, Kuan-Neng"

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2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
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Chou, Lei-Chun
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Huang, Teng-Chieh
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Wu, Shang-Lin
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Wang, Tang-Shuan
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
(2014-12-01)
Huang, Po-Tsang
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Wu, Shang-Lin
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Huang, Yu-Chieh
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Chou, Lei-Chun
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Huang, Teng-Chieh
Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with mu-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of mu-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 x 24 mu-probe array with embedded TSVs is fabricated on a 5 x 5 mm2 chip and bonded on the back side of the interposer. Thus, each channel contains 6 x 6 mu-probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus (mu-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 mu W for 16-channel neural sensing.
3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Chen, Shang-Chun
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Chang, Hsiang-Hung
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Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
3D Heterogeneous Integration Structure Based on 40 nm- and 0.18 mu m- Technology Nodes
(2015)
Hu, Yu-Chen
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Lin, Chun-Pin
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Hsieh, Yu-Sheng
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Chang, Nien-Shyang
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Gallegos, Anthony J.
In this paper, a simple process for high yield CMOS-compatible and heterogeneous integrated chip-to-chip structure without TSV is demonstrated. This scheme provides two chips consisted of the shortest interconnect path by Cu/Sn pillar bump and electroless nickel immersion gold (ENIG) pad bonding. One of the key technologies of 3D integration process is bump plating on the uneven topography. Since passivation layer covers the periphery of the top metal layer, subsequent electroplating process resulted to the increase in height of bump edge which is higher than bump center resulting in concave shape. A new and unique plating solution was developed to solve the issue during the electroplating pillar bump. Basic electrical characteristics including resistance and current leakage were investigated with reliability tests. The stable reliability tests results and excellent electrical performance show that the 3D heterogeneous integration structure is potentially applicable for 3D applications in the future.
A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITION
(2017-01-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Hu, Yu-Chen
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Wu, Shang-Lin
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You, Yan-Huei
To enhance the signal integrity of high-density neural-sensing signals, this work presents an implantable high spatial resolution mu-probe array with through-silicon via (TSV) 2.5D integration technology that realizes a miniaturized implantable device on flexible printed circuit (FPC) interposer. The proposed microsystem was composed of two 32-channel neural sensing chips and one radio frequency chip for neural signal processing. The mu-probe array can achieve better signal-to-noise ratio with neural-signal acquisition and processing circuit composed of a pseudo-resistor-based analog front-end amplifier. Moreover, a receiving antenna is also implemented on the backside of FPC for wireless data and power transmission. The feasibility of the proposed mu-probe array, Tx and Rx antenna, 32-channel neural sensing circuits in the 64-channel wireless microsystem have been successfully demonstrated for future integration and animal experiments.
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
(2015-02-01)
Chang, Chih-Wei
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Chou, Lei-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lee, Shih-Wei
We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.
A Flexible pH-Sensing Structure Using WO3/IrO2 Junction with Al2O3 Encapsulation Layer
(2013)
Kuo, Li-Min
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Chen, Kuan-Neng
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Chuang, Yi-Lin
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Chao, Shuchi
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電子物理學系
A diode-like current-voltage characteristic in response to hydrogen-ions based on a WO3/IrO2 diode coated with a membrane-like Al2O3 is reported. Microsensors fabricated with the oxides (IrO2 and WO3) will suffer from interference errors in pH-measurements due to their strong responses to environmental redox species. With ionic-conductive and insulation properties, the membrane can mediate the transport of released protons and block the electrons from redox species in solutions. Invoking proton-electron double injection, H+ and e(-) produce redox reactions, which control the conductivity and preserve the continuity of currents across the interface with a good sensitivity (0.168 mu A/pH) between pH = 2 to 12. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.004303ssl] All rights reserved.
A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
(2014-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Hsiang-Hung
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Lyu, Dian-Rong
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Hsu, Chao-Kai
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (similar to 3.6 mu m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
A Novel Bonding Approach and Its Electrical Performance for Flexible Substrate Integration
(2016-07-01)
Hu, Yu-Chen
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel bonding approach for flexible substrate vertical stacking is proposed in this paper. Unlike the traditional anisotropic conductive/non-conductive paste/film used in flexible substrate bonding, the metal thin film is adopted as bonding material in this approach. Experiment results show that the novel bonding approach has good electrical properties and reliability performances. The innovative bonding approach is considered a breakthrough of the traditional restrictions in flexible substrates, including I/O pitch, electrical reliability, and bonding conditions. This development is expected to contribute to the fabrication of future flexible substrate stacking.
A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node
(2015-12-01)
Hu, Yu-Chen
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Lin, Chun-Pin
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Chang, Yao-Jen
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Chang, Nien-Shyang
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Sheu, Ming-Hwa
A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.
A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration
(2018-02-01)
Lee, Shih-Wei
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Kuo, Shu-Chiao
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.
A Novel Sealing Redistribution Layer Approach for Through-Glass via Fabrication
(2017-03-01)
Lee, Shih-Wei
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Chang, Geng-Ming
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Chang, Ching-Yun
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Chen, Kuan-Neng
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電子工程學系及電子研究所
A sealing redistribution layer (RDL) approach for the interposer fabrication is developed to simplify the conventional bottom-up process flow. By using this approach, bottom-up plating can achieve the integration of Cu-filler plating and its bottom RDL simultaneously. In this paper, through-glass via in glass interposer or 3-D integration is fabricated using the proposed approach. The electrical measurement and reliability tests indicate that the proposed approach can be an attractive candidate for interposer fabrication with great performance.
A Novel Si-based X'tal Oscillator Device Using 3D Integration Technologies
(2014-01-01)
Shih, Jian-Yu
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Chen, Yen-Chi
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Chiu, Chih-Hung
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Lo, Chung-Lun
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Chen, Kuan-Neng
A novel Si-based X\'tal oscillator device (1.2 mm x 1.0 mm) is demonstrated by using 3D integration technologies. It is distinct from conventional X\'tal oscillator device with ceramics and metal lid. The novel Si-based X\'tal oscillator device shows no leakage path, and passes the hermetic encapsulation test and reliability investigation. In addition, the novel device shows the excellent electrical characteristics and provides the possibility to replace the conventional fabrication approach for the next generation products.
A precise pH microsensor using RF-sputtering IrO2 and Ta2O5 films on Pt-electrode
(2014-03-01)
Kuo, Li-Min
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Chou, Yi-Chia
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Chen, Kuan-Neng
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Lu, Chien-Chia
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Chao, Shuchi
In this study, an easily implemented surface modification scheme is reported employing Ta2O5 membrane which covers IrO2 electrode in response to H+ and eliminating redox species interference. Evidence shows that H+ can pass through Ta2O5 films and react with IrO2/Pt electrodes due to proton-electron double injection. A Ta2O5 membrane, an ionic conductor with an insulating property, blocks the transport of electrons generated from oxygen perturbation in the solution. The conduction of both electrons and protons preserve the current continuity across the interface. Owing to proton-electron double injection, IrO2 will be reduced to Ir(OH)(3) during pH detection. The [IrO2]/[Ir(OH)(3)] will remain constant and therefore the Nernstian electrode potential performs stably as a function of pH (-59.447 to -59.504 mV/pH, 2< pH <13). In addition, the proposed pH microsensor displayed high ion selectivity with respect to K+, Na+, and Li+, with log K-H,K-M values (similar to-12.4) and has a working lifetime over one week. (C) 2013 Elsevier B.V. All rights reserved.
A TSV-Based Bio-Signal Package With mu-Probe Array
(2014-02-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Huang, Po-Tsang
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Chang, Chih-Wei
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Chiang, Cheng-Hao
Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.
A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array
(2014-01-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Cheng, Chuan-An
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Huang, Po-Tsang
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Chang, Chih-Wei
Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.
A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
(2012-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Yao-Jen
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Chen, Peng-Shu
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Hwang, Yu-Jiau
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.
Adhesion and Material Properties Between Polyimide and Passivation Layers for Polymer/Metal Hybrid Bonding in 3-D Integration
(2019-03-01)
Lu, Cheng-Hsien
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Kho, Yi-Tung
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Chen, Chiao-Pei
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Tsai, Bin-Ling
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Chen, Kuan-Neng
This paper investigates polymer/metal hybrid bonding structure using conventional polyimide and modified polyimide-like material. Adhesion properties between bonding material and passivation layer were evaluated by four-point bending method, atomic force microscopy, water contact angle measurement, and X-ray photoelectron spectroscopy. Various annealing temperatures were applied to verify the reliability under thermal stress. The results show that the modified polyimide-like material with the curing temperature below 250 degrees C has better adhesion than the conventional polyimide. This modified polyimide material can be used in low-temperature hybrid bonding technology for advanced integration.
Adhesion Investigation Between Metal and Benzocyclobutene (BCB) Polymer Dielectric Materials in 3-D Integration Applications
(2014-09-01)
Shih, Jian-Yu
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Huang, Wen-Chun
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Ko, Cheng-Ta
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Yang, Zheng
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Hu, Sheng-Hsiang
In this paper, the interfacial adhesion strength between metal layer and benzocyclobutene (BCB) polymer dielectric in 3-D integration applications is investigated. The effects of layer thickness, layer stacking order, and additional adhesion layer of titanium (Ti) layer between copper (Cu) and BCB polymer are investigated. Surprisingly, the conventional titanium adhesion layer commonly used in the semiconductor industry weakens the interfacial adhesion strength between copper and BCB. Additionally, to figure out the interfacial adhesion mechanisms, the interfacial structures probed by sum-frequency-generation vibrational spectroscopy are correlated to the adhesion strengths measured from corresponding sample interfaces. It is found that ordered C-H groups at the metal/BCB interface, such as titanium/BCB or molybdenum/BCB, lead to weak interfacial adhesion strength, whereas disordered interfaces, i.e., copper/BCB, lead to strong interfacial adhesion strength.
Adhesion Properties of Electroplating Process Between Polyimide and Metal Layer for Polymer/Metal Hybrid Bonding
(2020-01-01)
Lu, Cheng-Hsien
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Yang, Yi-Lun
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Chen, Chiao-Pei
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Tsai, Bin-Ling
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Chen, Kuan-Neng
This article investigates the adhesion properties between the polyimide layers and the Ti/Cu layer after the electroplating process. The adhesion strength was evaluated by the four-point bending system, and the influence factors were confirmed by using different electroplating times and currents. The fracture interface after the four-point bending measurement was characterized, and the interface spectrum between the polyimide and the Ti/Cu layer was analyzed. The results showed that the modified polyimide-like material has better adhesion performance than the conventional polyimide. Moreover, the mechanism of degradation was proposed. As a result, the modified polyimide-like material can be applied in electroplating, a redistribution layer (RDL) formation, and packaging at the back-end-of-line processes.