Browsing by Author "Chen, Kun-Ming"

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A Miniature 92-95 GHz On-chip Slow-wave Branch-line Coupler
(2018-01-01)
Chen, Yi-Tang
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Chiu, Chia-Sung
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Chuang, Chia-Wei
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Chen, Kun-Ming
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Huang, Guo-Wei
A miniature 92-95 GHz on-chip branch-line coupler (BLC) employing a slow-wave microstrip line is proposed herein. The ground metal plane beneath the signal line is periodically slotted, and the coupler can be highly miniaturized owing to the short wavelength characteristic of the transmission line with slow-wave structure. The size of the slow-wave BLC is 250 mu m X 250 mu m, which is 39% of the size of conventional BLCs.
A simple extraction method for parasitic series resistances in GaN HEMTs considering non-quasi-static effects
(2019-05-01)
Nagarajan, Venkatesan
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Chen, Kun-Ming
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Wang, Huan-Chung
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Singh, Sankalp Kumar
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Anandan, Deepak
A simple technique for extracting the bias-dependent parasitic series resistances of the GaN-based high electron mobility transistor (HEMT) is demonstrated in this paper. With considering the non-quasi-static effect in devices, new analytical Z-parameter formulations are derived to determine parasitic resistances using the curve-fitting algorithm. More accuracy parasitic resistances can be obtained over a wide fitting frequency range compared to the conventional method which ignores the non-quasi-static effect. Here the intrinsic parameters are then calculated directly from intrinsic Y-parameters after de-embedding the parasitic elements in the small-signal equivalent circuit. An excellent agreement between the measured and simulated S-parameters from 100 MHz to 40 GHz is achieved, which validates the feasibility of our method for extracting the bias-dependent parasitic resistances.
An analysis of base current effect on the anomalous dip of scattering parameter S(12) in SiGeHBTs
(2005)
Chen, Han-Yu
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chang, Chun-Yen
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電子工程學系及電子研究所
In this paper, the anomalous dip in scattering parameters S(12) of SiGe HBTs is explained quantitatively for the first time. It was found that under constant collector-emitter voltage (V(CE)), an increase of base current (which corresponds to an increase of base-emitter capacitance (C pi) enhances the anomalous dip.
Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs
(2018-10-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chen, Hsiu-Chih
Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs.
Analysis of temperature effects on high-frequency characteristics of RF lateral-diffused metal-oxide-semiconductor transistors
(2008-04-01)
Hu, Hsin-Hui
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chien, Alex
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Cheng, Eric
In this work, the effects of temperature on the DC and RF characteristics of lateral-diffused metal-oxide-semi conductor (LDMOS) transistors were studied. Devices with different layout structures were fabricated using a 40 V LDMOS process. The temperature coefficients of the threshold voltage and channel mobility are negative and their values are similar for devices with fishbone and ring structures. In addition, we found that both the cutoff frequency (f(T)) and the maximum oscillation frequency (f(max)) decrease with increasing temperature. The variations of f(T) with different temperatures are not only affected by the change in transconductance but also affected by the drain resistance. Finally, the temperature behaviors of S-parameters were measured, and the ring structure showed less S(22) variation with different temperatures than the fishbone structure. We extracted the model parameters of the devices to explain this observation.
Capacitance Characteristics Improvement and Power Enhancement for RF LDMOS Transistors Using Annular Layout Structure
(2011-03-01)
Chiu, Chia-Sung
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chen, Ming-I.
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Yang, Yu-Chi
This paper presents an annular-structure lateral-diffused metal-oxide-semiconductor (LDMOS) RF transistor using a 0.5-mu m LDMOS process. This paper also examines the dc, small-signal, and large-signal characteristics of RF LDMOS transistors with different closed structures. In particular, the problem of evaluating the LDMOS aspect ratio for annular structure is addressed. The capacitance characteristics improvement in the LDMOS device design using the annular structure was also investigated. The power gain and efficiency of annular structure give nearly 5% enhancement compared to the traditional structure with 80-mu m gatewidth at 1.9 GHz. Results show that the annular structure appears to be a better layout design for RF LDMOS transistors.
Channel Thickness Effect on High-Frequency Performance of Poly-Si Thin-Film Transistors
(2013-08-01)
Chen, Kun-Ming
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Tsai, Tzu-I
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Lin, Ting-Yao
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Lin, Horng-Chih
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Chao, Tien-Sheng
In this letter, we present the high-frequency performances of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a nominal gate length of 0.22 mu m. Owing to the short gate length and adoption of salicide process, cutoff frequency (f (T)) of 17 GHz and maximum oscillation frequency of similar to 21 GHz are obtained. The result suggests that the poly-Si TFT technology is applicable to RF integrated circuits up to 2 GHz. In addition, we also investigate the effects of channel thickness on the high-frequency characteristics of poly-Si TFTs. We find that the variation of f (T) with channel thickness is mainly due to the change in transconductance.
Characterization of Annular-Structure RF LDMOS Transistors Using Polyharmonic Distortion Model
(2009)
Chiu, Chia-Sung
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Chen, Kun-Ming
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Huang, Guo-Wei
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Hsiao, Chih-Hua
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Liao, Kuo-Hsiang
An annular-structure lateral-diffused metal-oxide semiconductor (LDMOS) RF transistor with polyharmonic distortion (PHD) model characterized by nonlinear vector network analyzer is described in this paper. The devices were fabricated using a 0.5 mu m LDMOS process. The DC, small-signal, and large-signal characteristics of RF LDMOS transistors with annular-structures were also studied in this work. Using the PHD model, the accuracy of intermodulation and time waveform is verified. Furthermore, the model via X-parameter shows good agreement without optimization.
Characterization of RF lateral-diffused metal-oxide-semiconductor field-effect transistors with different layout structures
(2007-04-01)
Hu, Hsin-Hui
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chang, Chun-Yen
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Lu, Yii-Chian
The DC and RF characteristics of lateral-diffused metal-oxide-semi conductor (LDMOS) transistors with different layout structures were studied. The devices were fabricated using a 0.5 mu m LDMOS process. The ring and fishbone structures, which are used widely in power devices, were designed and analyzed. We found that the. transconductance, on-resistance, cutoff frequency and maximum oscillation frequency were improved using the ring structure, due to a larger equivalent W/L and lower drain parasitic resistance. In addition, the self-heating effect of LDMOS transistors was also investigated by measuring the pulsed current-voltage (I-V) and pulsed RF characteristics. From the measured results, the ring structure appeared to be a better layout design for RF LDMOS transistors.
Comprehensive Noise Characterization and Modeling for 65-nm MOSFETs for Millimeter-Wave Applications
(2010-04-01)
Wang, Sheng-Chun
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Su, Pin
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Chen, Kun-Ming
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Liao, Kuo-Hsiang
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Chen, Bo-Yuan
Using an external tuner-based method, this paper demonstrates a complete millimeter-wave noise characterization and modeling up to 60 GHz for 65-nm MOSFETs for the first time. Due to channel length modulation, the channel noise continues to increase and remains the most important noise source in the millimeter-wave band. Our experimental results further show that, with the downscaling of channel length, the gate resistance has more serious impact on the high-frequency noise parameters than the substrate resistance even in the millimeter-wave frequency.
DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries
(2019-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Shiao, Yu-Shao Jerry
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Lin, Chuang-Ju
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Huang, Guo-Wei
In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f(T)) and maximum oscillation frequencies (f(max)) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f(T) and f(max) are around 25 GHz and 30 GHz, respectively. The high f(T) and f(m)(ax) as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications. (C) 2019 The Japan Society of Applied Physics
Design for integration of RF power transistors in 0.13 mu m advanced CMOS technology
(2007)
Huang, Sheng-Yi
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chang, Chun-Yen
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Hung, Cheng-Chou
An RF power MOSFET was proposed and manufactured in a standard 0.13 mu m CMOS technology. Without adding additional masks, cost and process, the breakdown voltage can be improved by using the N-well and shallow-trench-isolation processes to form a drift n(-) region. The breakdown voltage was 4.3V at gate bias of 1.2V. The cutoff frequency and maximum oscillation frequency were 68GHz and 87GHz, respectively. In addition, the power gain, output power and power-added efficiency were 16.8dB, 15.9dBm and 43.5%, respectively, at 2.4GHz. Good RF linearity also addressed OIP3 of 28.6dBm. The presented RF power transistor is cost effectively and can be applied into the power amplifier integration for RF SoC.
Effect of NH(3) Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-kappa Dielectric nMOSFETs
(2011-03-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Lin, Cheng-Li
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Yeh, Wen-Kuan
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Huang, Guo-Wei
The effects of post-NH(3) plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high-kappa/metal-gate n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and 1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk-and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-kappa layer. In this paper, appropriate post-NH(3) plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high-kappa/metal-gate nMOSFET with a Gd cap layer.
Effect of NH3 Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-kappa Dielectric nMOSFETs
(2011-03-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Lin, Cheng-Li
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Yeh, Wen-Kuan
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Huang, Guo-Wei
The effects of post-NH3 plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high-kappa/metal-gate n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and 1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk-and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-kappa layer. In this paper, appropriate post-NH3 plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high-kappa/metal-gate nMOSFET with a Gd cap layer.
High-frequency performances of superjunction laterally diffused metal-oxide-semiconductor transistors for RF power applications
(2016-04)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chang, Edward Yi
This paper presents the dc and high-frequency performances of laterally diffused metal-oxide-semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-mu m CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers. (C) 2016 The Japan Society of Applied Physics
High-frequency performances of superjunction laterally diffused metal-oxide-semiconductor transistors for RF power applications
(2016-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chang, Edward Yi
This paper presents the dc and high-frequency performances of laterally diffused metal-oxide-semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-mu m CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers. (C) 2016 The Japan Society of Applied Physics
Impact of Body Bias on the High Frequency Performance of Partially Depleted SOI MOSFETs
(2008)
Huang, Guo-Wei
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Chen, Kun-Ming
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Chen, Han-Yu
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Huang, Chi-Huan
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Chang, Chun-Yen
Impact of Highly Compressive Interlayer-Dielectric-SiN(x) Stressing Layer on 1/f Noise and Reliability of SiGe-Channel pMOSFETs
(2010-12-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Liao, Wen-Shiang
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Huang, Guo-Wei
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Huang, Fon-Shan
The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiN(x) stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.
Impact of Highly Compressive Interlayer-Dielectric-SiNx Stressing Layer on 1/f Noise and Reliability of SiGe-Channel pMOSFETs
(2010-12-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Liao, Wen-Shiang
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Huang, Guo-Wei
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Huang, Fon-Shan
The 1/f noise and reliability of SiGe-channel pMOSFETs with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have been studied in this letter. The SiGe-channel devices with a highly compressive CESL layer have higher drain current and lower 1/f noise than the conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the highly compressive CESL layer. By examining the effective oxide-trap densities under hot-carrier instability stress, we find that the incorporated hydrogen in gate oxide during CESL layer deposition may play an important role on the 1/f noise and device reliability.
Investigation of High-Frequency Noise Characteristics in Tensile-Strained nMOSFETs
(2011-03-01)
Wang, Sheng-Chun
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Su, Pin
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Chen, Kun-Ming
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Chen, Bo-Yuan
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Huang, Guo-Wei
For the first time, the high-frequency noise behavior of tensile-strained n-channel metal-oxide-semiconductor field-effect transistors, including their temperature dependency, is experimentally examined. Our experimental results show that with similar saturation voltages, the strained device is found to have larger channel noise than the control device at the same bias point. For given direct-current power consumption, however, due to enhanced transconductance, the strained device has better small-signal behaviors (higher f(t) and f(max)) and noise characteristics (smaller NF(min) and R(n)) than the control device.