Browsing by Author "Chen, Liang-Gee"

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A 100 MHZ 1920x1080 HD-PHOTO 20 FRAMES/SEC JPEG XR ENCODER DESIGN
(2008)
Chien, Ching-Yen
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Huang, Sheng-Chieh
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Lin, Shih-Hsiang
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Huang, Yu-Chieh
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Chen, Yi-Cheng
A JPEG XR chip for HD-Photo is implemented with 25 MM area in TSMC 0.18um CMOS 1P6M technology at 100MHz According to the simulation results, the 4:4:4 1920x1080 HD-Photo 20 frames/sec can be encoded smoothly.
Architecture design of full HD JPEG XR encoder for digital photography applications
(2008-08-01)
Pan, Chia-Ho
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Chien, Ching-Yen
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Chao, Wei-Min
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Huang, Sheng-Chieh
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Chen, Liang-Gee
To satisfy the high quality image compression requirement, the new, JPEG XR compression standard is introduced. The analysis and architecture design with VLSI architecture of JPEG XR encoder are proposed in this paper which can encode 4:4:4 1920 x 1080 high definition photo in smooth. According to the simulation results, the throughput of the proposed design can encode 44.2 M samples/sec. This design can be used for digital photography applications to achieve low computation, low storage, and high dynamical range features.
NEUSORT2.0: A Multiple-channel Neural Signal Processor with Systolic Array Buffer and Channel-interleaving Processing Schedule
(2008)
Chen, Tung-Chien
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Yang, Zhi
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Liu, Wentai
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Chen, Liang-Gee
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交大名義發表
An emerging class of neuroprosthetic devices aims to provide aggressive performance by integrating more complicated signal processing hardware into the neural recording: system with a large amount of electrodes. However, the traditional parallel structure duplicating one neural signal processor (NSP) multiple times for multiple channels takes a heavy burden on chip area. The serial structure sequentially switching the processing task between channels requires a bulky memory to store neural data and may has a long processing delay. In this paper, a memory hierarchy of systolic array buffer is proposed to support signal processing interleavingly channel by channel in cycle basis to match up with the data flow of the optimized multiple-channel frontend interface circuitry. The NSP can thus be tightly coupled to the analog frontend interface circuitry and perform signal processing for multiple channels in real time without any bulky memory. Based on our previous one-channel NSP of NFUSORT1.0 [1], the proposed memory hierarchy is realized on NFUSORT2.0 for a 16-channel neural recording system. Compared to 16 of NEUSORT1.0, NEUSORT2.0 demonstrates a 81.50% saving in terms of area x power factor.
Pipelined Arithmetic Encoder Design for Lossless JPEG XR Encoder
(2009)
Chien, Ching-Yen
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Huang, Sheng-Chieh
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Pan, Chia-Ho
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Fang, Ce-Min
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Chen, Liang-Gee
With rapid progress of sensors, display devices, and computing engines, image application exists everywhere. High quality, high compression rates of digital image and low computational cost are important factors of consumer electronics. In this paper, we proposed a 4:4:4 lossless JPEG XR encoder design. In JPEG XR encoder, entropy coding is a critical module of encoder. We proposed a well-defined timing schedule of pipeline architecture to speed up the entropy encoding, which is the most computationally intensive part in JPEG XR encoder. This design can be used for the digital photography applications to achieve the low complexity of computation, low storage, and high dynamic range.
Real-time free viewpoint rendering system for face-to-face video conference
(2008)
Pan, Chia-Ho
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Huang, Sheng-Chieh
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Chang, Yu-Lin
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Lian, Chung-, Jr.
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Chen, Liang-Gee
Face-to-face communication experience plays an important role in videoconference applications. In this paper, we propose view angle rectification and view synthesis methods to generate the preferred view at observer\'s side. The proposed free viewpoint rendering system achieves face-to-face communication experience for real-time videoconference application.
SCALABLE VIDEO ADAPTATION OPTIMIZATION USING SOFT DECISION SCHEME
(2008)
Pan, Chia-Ho
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Huang, Sheng-Chieh
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Lee, I-Hsien
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Lian, Chung-, Jr.
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Chen, Liang-Gee
Video transmission over a heterogeneous network suffers a condition that it has required to satisfy many different constraints because of the variety limitations of client equipments and preferences of each user. In this condition, the video stream should have the flexibility feature. Scalable video coding is one of the solutions to serve this condition. In order to provide a better flexibility on scalability feature, more than one combination with video spatial size, temporal frame rate, and visual quality resolution are utilized. It is difficult to adapt the appropriate relation between the various combinations and user preference. In this paper, we propose an objectivity-derived algorithm with soft decision scheme for serving scalable video adaptation. This method can be used in existing equipments without much computation overhead. This useful and simple solution is not only a practical way in scalable video adaptation design, but also an efficient scheme of achieving subjective satisfaction.
VLSI Architecture of Leading Eigenvector Generation for On-chip Principal Component Analysis Spike Sorting System
(2008)
Chen, Tung-Chien
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Liu, Wentai
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Chen, Liang-Gee
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交大名義發表
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National Chiao Tung University
On-chip spike detection and principal component analysis (PCA) sorting hardware in an integrated multi-channel neural recording system is highly desired to ease the bandwidth bottleneck from high-density microelectrode array implanted in the cortex. In this paper, we propose the first leading eigenvector generator, the key hardware module of PCA, to enable the whole framework. Based on the iterative eigenvector distilling algorithm, the proposed flipped structure enables the low cost and low power implementation by discarding the division and square root hardware units. Further, the proposed adaptive level shifting scheme optimizes the accuracy and area trade off by dynamically increasing the quantization parameter according to the signal level. With the specification of four principal components/channel, 32 samples/spike, and nine bits/sample, the proposed hardware can train 312 channels per minute with 1MHz operation frequency. 0.13 mm(2) silicon area and 282 mu W power consumption are required in 90 nm 1P9M CMOS process.