Browsing by Author "Chen, Lun-Chun"

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Fabrication, characterization and simulation of Omega-gate twin poly-Si FinFET nonvolatile memory
(2013-07-22)
Yeh, Mu-Shih
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Wu, Yung-Chun
;
Hung, Min-Feng
;
Liu, Kuan-Cheng
;
Jhan, Yi-Ruei
This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Omega-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Omega-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 10(4) program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.
High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer
(2012-04-01)
Chen, Hung-Bin
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Wu, Yung-Chun
;
Chen, Lun-Chun
;
Chiang, Ji-Hong
;
Yang, Chao-Kan
This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10(4) s at 150 degrees C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.
Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method
(2019-01-01)
Chen, Lun-Chun
;
Chen, Hung-Bin
;
Chang, Yu-Shuo
;
Lin, Shih-Han
;
Han, Ming-Hung
A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention.
Poly-Si Nanowire Nonvolatile Memory With Nanocrystal Indium-Gallium-Zinc-Oxide Charge-Trapping Layer
(2010-12-01)
Chen, Lun-Chun
;
Wu, Yung-Chun
;
Lin, Tien-Chun
;
Huang, Jyun-Yang
;
Hung, Min-Feng
This letter introduces a polycrystalline silicon (poly-Si) thin-film nonvolatile memory (NVM) with a nanocrystal (NC) indium-gallium-zinc-oxide (IGZO) charge-trapping layer. Experimental results indicate that this NVM exhibits high and symmetric program/erase speeds through the Fowler-Nordheim tunneling mechanism. The memory window loss of the NVM with NC IGZO charge-trapping layer is 25% after 10(4) s at 85 degrees C due to deep quantum well, as well as high-density and deep trap sites in NC IGZO charge-trapping layer. Accordingly, a poly-Si thin-film transistor with NC IGZO charge-trapping layer is promising for NVM applications.