Browsing by Author "Chen, M. C."

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High-density nano-pillar SiOx-based resistive switching memory using nano-sphere lithography to fabricate a one diode - one resistor (1D-1R) architecture
(2014-01-01)
Chang, Y. F.
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Ji, L.
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Chen, Y. C.
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Zhou, F.
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Tsai, T. M.
A highly compact, one diode - one resistor (1D-1R) nano-pillar device architecture has been demonstrated using nano-sphere lithography (NSL) to fabricate SiOx-based resistive switching (RS) memory. The intrinsic SiOx-based resistive switching element and Si-based PN diode are self-aligned on the epitaxial silicon wafer using NSL and a deep-Si-etch process without using conventional photolithography. The DC electrical performance, an AC pulse response in the 50 ns regime, capability for multi-bit operation, and high readout margin immunity for sneak path issue demonstrate good potential for high-speed nonvolatile memory (NVM). The NSL fabrication process is an efficient, economical approach to enable large-scale patterning of 1D-1R architectures while providing excellent NVM performance for future applications.
Improvement of luminescence from Si nanocrystals with thermal annealing in CO2
(2008-01-15)
Yang, M. D.
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Chu, A. H. M.
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Shen, J. L.
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Huang, Y. H.
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Yang, T. N.
Photoluminescence (PL) of Si nanocrystals with annealing in CO2 was studied using the continuous and time-resolved PL measurements. The PL intensity enhances as annealing temperature increases, which is attributed to passivation of the nonradiative recombination centers. As the annealing temperature is 950 degrees C the PL intensity has a maximum value, which increases about a factor of 3 than that of the untreated sample. Based on the emission energy dependence of the PL decay time, the depth of carrier localization is found to increase after the annealing in CO2. We suggest that the oxygen atoms desorbed from CO2 diffuse to react with Si nanocrystals and introduce localized states at the Si/SiO2 interface. (C) 2007 Elsevier B.V. All rights reserved.
Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory
(2016)
Su, P. C.
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Chung, Y. T.
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Chen, M. C.
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Wang, Tahui
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電子工程學系及電子研究所
Factors affecting SET-disturb failure time (tau(f)) in a tungsten oxide resistive switching memory including SET/RESET cycling stress, resistance window in operation and SET-disturb voltage are investigated. A SET-disturb failure time in high resistance state (HRS) may degrade by orders of magnitude in a post-cycling cell. The degradation is attributed to the formation of a current percolation path of cycling stress-generated traps. A one-dimensional percolation model is proposed for the tau(f) degradation. The dependence of tau(f) on resistance window in operation is characterized. We find that tau(f) is greatly affected by the current level of LRS. The strong LRS dependence of tf is attributed to a small Weibull slope of tau(f). In addition, we perform statistical characterizations of tau(f) at different SET-disturb voltages. A relationship between tau(f) and a SET-disturb voltage in a stressed cell is given.
Investigation of Random Telegraph Noise Amplitudes in Hafnium Oxide Resistive Memory Devices
(2014-01-01)
Chung, Y. T.
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Liu, Y. H.
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Su, P. C.
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Cheng, Y. H.
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Wang, Tahui
Statistical characterization of two-level random telegraph noise (RTN) amplitude distribution in a hafnium oxide resistive memory has been performed. We find that two-level RTN in HRS exhibits a large amplitude distribution tail, as compared to LRS. To investigate an RTN trap position in a hafnium oxide film, we measure the dependence of electron capture and emission times of RTN on applied read voltage. A correlation between an RTN trap position and RTN amplitude is found. A quasi-two-dimensional RTN amplitude simulation based on trap-assisted electron sequential tunneling is developed. Our study shows that RTN traps in a rupture region of a hafnium oxide film are responsible for an RTN large-amplitude tail in HRS mostly.
Optical studies of InN epilayers on Si substrates with different buffer layers
(2007-12-01)
Yang, M. D.
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Shen, J. L.
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Chen, M. C.
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Chiang, C. C.
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Lan, S. M.
We have investigated the photoluminescence (PL) and time-resolved PL from the InN epilayers grown on Si substrates with different buffer layers. The narrowest value of the full width at half maximum of the PL peak is 52 meV with the AlN/AlGaN/GaN triple buffer layer, which is better than previous reports on similar InN epilayers on Si substrates. Based on the emission-energy dependence of the PL decays, the localization energy of carriers is also the least for the InN with a triple buffer layer. According to the x-ray diffraction measurements, we suggest that the reduced lattice mismatch between the InN epilayer and the top buffer layer is responsible for improvement of sample quality using the buffer-layer technique. (c) 2007 American Institute of Physics.