Browsing by Author "Chen, MC"

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A cross-layer cost-function based rate adaptation mechanism for the WCDMA system with multi-class services by transport format selection
(2005-06-01)
Wang, LC
;
Chen, MC
;
Chen, YC
;
電信工程研究所
;
Institute of Communications Engineering
The growing demand of high speed multi-class data transmissions poses new challenges on wireless networks. The major objectives of the next generation wireless networks include: (1) achieving high data throughput in the fast varying wireless channel; (2) transmitting multi-class data by service multiplexing; and (3) controlling the delay for delay sensitive service. To achieve these goals, in the context of wideband code division multiple access (WCDMA) system, we propose a cost-function based rate adaptation mechanism by taking account of both physical layer channel impacts and higher layer performance parameters, such as buffer occupancy and service priority. We implement this cross-layer rate mechanism by exploiting the transport format (TF) selection procedure in the medium access control (MAC) layer of the WCDMA system. Through the proposed cross-layer cost function, the TF selection procedure can dynamically adapt suitable spreading factors every transmission time interval (TTI), usually 10-80 ms. Through simulations in a flat Rayleigh fading channel, we show that the proposed cross-layer cost-function based rate adaptation mechanism can effectively improve throughput and reduce the buffer occupancy for multi-class services for the WCDMA system at the cost of slightly higher power efficiency. Copyright (c) 2005 John Wiley & Sons, Ltd.
A joint physical layer multi-state rate adaptation and cost-function based MAC scheduling for the WCDMA system
(2003)
Wang, LC
;
Chen, MC
;
Chen, YC
;
交大名義發表
;
National Chiao Tung University
This paper presents a joint physical layer multi-state rate adaptation algorithm combined with MAC scheduling for the WCDMA system. According to the cumulative distribution function of the received signal to noise ratio (SNR), our proposed multi-state rate adaptation scheme determines a set of state transition thresholds to dynamically adjust spreading factors via the transport format (TF) selection procedures in the MAC layer. Moreover, we proposed a cost function based TF selection procedures to incorporate many important factors in both the MAC layer and physical layer, such as service priority, buffer occupancy, and radio link quality. Through a cross-layer design in both the two layers, the proposed cost function based transport format selection procedures can effectively enhance throughput, save power, and guarantee service fairness for the WCDMA system.
A new tungsten gate metal oxide semiconductor capacitor using a chemical vapor deposition process
(1997-01-01)
Yeh, WK
;
Shiau, YC
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new process for tungsten gate metal oxide semiconductor (MOS) capacitors has been developed using chemical vapor deposition (CVD) of tungsten on a thin poly-Si layer of appropriate thickness. The poly-Si acts as a sacrificial layer and is consumed during the CVD of tungsten (W). This process yields a nearly pure W metal gate after Sill, reduction of WF6 at 300 degrees C. Compared with sputtered tungsten films, the CVD tungsten film has lower resistivity and lower intrinsic film stress. In addition, the CVD tungsten metal gate MOS capacitor has a lower interface state density (D-it) and a higher charge-to-breakdown (Q(bd)), than sputter-deposited tungsten gate MOS capacitors.
A novel two-step annealing technique for the fabrication of high performance low temperature poly-Si TFTs
(2003-08-01)
Fan, CL
;
Chen, MC
;
Chang, Y
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low temperature processed (LTP) poly-Si thin film transistors (TFTs) fabricated with a poly-Si film crystallized by a novel two-step annealing (NTSA) technique were investigated and compared with those using conventional solid phase crystallization (SPC) and excimer laser annealing (ELA) schemes. The NTSA scheme is characterized by the combination of an excimer laser induced formation of nucleation centers and a short-time low temperature furnace annealing (about 6 h at 600degreesC) creating clear crystalline grains with very few in-grain defects. The LTP poly-Si TFTs fabricated with a NTSA poly- Si film not only exhibit a better performance but also significantly shorten the crystallization time as compared to those fabricated using the conventional SPC (about 20 h or longer at 600degreesC). In addition, the uniformity of the device characteristics for the devices using the NTSA scheme is superior to that using the ELA scheme and is comparable to that using the SPC scheme. (C) 2003 The Electrochemical Society.
A symbolic/neural hybrid approach to multiple shape recognition
(1996)
Chen, MC
;
Liu, YT
;
應用藝術研究所
;
Institute of Applied Arts
An efficient improvement for barrier effect of W-filled contact
(1996-02-01)
Yeh, WK
;
Chan, KY
;
Chang, TC
;
Tsai, MH
;
Chen, SH
A post chemical vapor deposition of tungsten (CVD-W) treatment by N-2 plasma is proposed to suppress the WAl12 formation during subsequent thermal annealing, which improves the thermal stability of W-filled contact. Selective CVD-W is employed to fill the contact hole. Following W deposition, in situ N-2 plasma treatment is performed prior to Al alloy metallization. It is shown that this post CVD-W treatment efficiently suppresses the formation of WAl12, resulting in an improvement of the barrier capability of W-filled contact.
Annealing effect on boron high-energy-ion-implantation-induced defects in
(2004-08-01)
Hsu, WC
;
Liang, MS
;
Chen, SC
;
Chen, MC
;
電子工程學系及電子研究所
In this work, we investigate the annealing effect on defects in Si induced by boron high-energy (1.5 MeV) ion implantation with respect to implantation dose (1.1 X 10(13) and 5 x 10(13) cm(-2)) as well as annealing scheme [rapid thermal annealing (RTA) and furnace annealing (FA)]. The higher dose implantation resulted in more serious degradation of the minority carrier generation lifetime in the implanted layers. Also, the degree of lifetime recovery by either RTA or FA was very limited with the higher dose implantation, presumably due to the presence of the implantation-induced dislocations. The degradation of the lifetime in the lower dose-implanted sample could be significantly recovered by the annealing process, particularly the RTA scheme; this is presumably because RTA has a better ability to reduce the implantation-induced interstitials.
Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias
(2003-04-01)
Tsai, CW
;
Chen, MC
;
Ku, SH
;
Wang, TH
;
電子工程學系及電子研究所
Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel thus substantially increasing channel hot electron energy. Measured hot electron gate-current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten time's more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.
Barrier capabilities of selective chemical vapor deposited W films and WSiN/WSix/W stacked layers against Cu diffusion
(1999-02-01)
Wang, MT
;
Chen, LJ
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work investigates the barrier capability of W layers as well as WSiN/WSix/W stacked layers against Cu diffusion. The VV layers were selectively chemical vapor deposited (CVD) in contact holes to a thickness of about 450 nm using SiH4 reduction of WF6. We found that the CVD-W layers functioned as effective barriers against Cu diffusion, and the Cu/W(450 nm)/p(+)-n junction diodes were able to sustain a 30 min furnace annealing up to 650 degrees C without causing degradation in electrical characteristics. The use of WSiN/WSix/W stacked layers as diffusion layers further improved the thermal stability of Cu/WSiN/WSix/W(450 nm)p(+)-n junction diodes to at least 700 degrees C. The WSix layers were deposited by CVD to a thickness of 75 nm using SiH4/WF6 chemistry, and the subsequent in situ N-2 plasma treatment produced a very thin layer of WSiN on the WSix surface. This thin WSiN layer was very thermally stable and effective in suppressing Cu diffusion, failure of barrier capability for the W films was presumably due to interdiffusion of Cu and Si along grain boundaries of the W films, and the interdiffusion was probably enhanced by the formation of WSi2, The formation of WS(i)2 consumed the W layer and Si substrate, resulting in a volume change in barrier layer, which, in turn, developed local defects, such as microcracks and stress-induced weak points, and thus provided fast paths for Cu diffusion. (C) 1999 The Electrochemical Socity S0013-4651(98)04-036-1. All rights reserved.
Barrier characteristics of PECVD alpha-SiC : H dielectrics
(2001)
Chiang, CC
;
Wu, ZC
;
Wu, WH
;
Chen, MC
;
Ko, CC
This work investigates the thermal stability and barrier characteristics of three species of PECVD alpha-SiC:H dielectric films with dielectric constants between 3.5 and 5.4. It is found that the dielectric constant decreases with increasing content of carbon in the alpha-SiC:H film. All of the three specie's of alpha-SiC:H films are thermally stable at temperatures of up to 500degreesC. However, degraded barrier capability and moisture resistance were observed for the alpha-SiC:H film with a k value around 3.5, which has a C/Si atomic ratio of 0.875. This is presumably attributed to poorly crosslinked molecular structure and porosity enhancement by the abundant amount of carbon in the alpha-SiC:H film.
Barrier properties of very thin Ta and TaN layers against copper diffusion
(1998-07-01)
Wang, MT
;
Lin, YC
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Diffusion barrier properties of very thin sputtered Ta and reactively sputtered TaN films used as a barrier layer between Cu and Si substrates were investigated using electrical measurement and materials analysis. The Cu/Ta/p(+)-n junction diodes with the Ta barrier of 5, 10, and 25 nm thicknesses were able to sustain a 30 min thermal annealing at temperatures up to 450, 500, and 550 degrees C, respectively, without causing degradation to the device's electrical characteristics. The barrier capability of Ta layer can be effectively improved by incorporation of nitrogen in the Ta film using reactive sputtering technique. For the Cu/TaN/p(+)-n junction diodes with the TaN barrier of 5,10, and 25 nm thicknesses, thermal stability was able to reach 500, 600, and 700 degrees C, respectively. We found that failure of the very thin Ta and TaN barriers was not related to Ta silicidation at the barrier/Si interface. Failure of the barrier layer is presumably due to Cu diffusion through the barrier layer during the process of thermal annealing via local defects, such as grain boundaries and stress-induced weak points.
Characteristics of copper films deposited on H(2)-plasma-treated TaN substrate by chemical vapor deposition
(2002-09-01)
Lin, CL
;
Chen, PS
;
Chang, CL
;
Chen, MC
;
電子工程學系及電子研究所
This work investigates the chemical vapor deposition Cu films deposited on the TaN substrate with and without an H(2)-plasma treatment prior to Cu film deposition and the effect of postdeposition thermal annealing. The Cu films deposited on the H(2)-plasma-treated TaN substrate have a number of favorable properties over the films deposited on the TaN substrate without the plasma treatment. These include an increased (111)-preferred orientation, smoother film surface, and a larger effective deposition rate. However, the Cu films deposited on the H(2)-plasma-treated substrate have a higher electrical resistivity, presumably due to the smaller, grain size. The postdeposition thermal annealing enhanced the (111)-preferred orientation and decreased the resistivity of the as-deposited Cu films. We presume that the H(2)-plasma treatment, resulted in a dense and uniform distribution of hydrogen radicals adsorbed on the substrate surface, leading to the shortening of incubation time and the formation of Cu films with a smoother surface and enhanced (100)-preferred orientation. A combined process including H(2)-plasma substrate treatment prior to Cu film deposition and postdeposition thermal annealing at an appropriate temperature in N(2) ambient, is proposed for the advantage of low-resistivity and high (111)-oriented Cu film deposition. (C) 2002 American Vacuum Society.
Chemical mechanical polishing for selective CVD-W
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
(1997-10-30)
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemical mechanical polishing for selective CVD-W
(1997-10-30)
Wang, MT
;
Yeh, WK
;
Tsai, MS
;
Tseng, WT
;
Chang, TC
This work investigates chemical mechanical polishing (CMP) for W-filled contact holes, vias, and trenches by selective chemical vapor deposition. A novel process that combines the CMP technique with selective chemical vapor deposition of tungsten (CVD-W) was employed to remove nail heads due to overgrowth and W-particles on the surface of dielectric due to selectivity loss. The overfilled nail heads and the selectivity loss can be completely removed with very low down-pressure (3 psi) in a very short polishing time (30 s). This indicates that the novel process is very promising for ULSI multilevel interconnection application. The removal rate selectivities of W to thermal oxide, PECVD-TEOS, and BPSG were found to be 47:1, 30:1 and 15:1, respectively, while the selectivities of W to the barrier metals of TiW, Ti and Ta were determined to be 0.6:1, 6:1 and 28:1, respectively. (C) 1997 Elsevier Science S.A.
Chemically vapor deposited Cu films on Ar-plasma-treated TiN substrate
(2002-01-01)
Lin, CL
;
Chen, PS
;
Chen, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Chemically vapor deposited (CVD) Cu films on TiN substrates with and without Ar plasma treatment prior to Cu film deposition and the effects of postdeposition thermal annealing were investigated. Cu films deposited on an Ar-plasma-treated TiN substrate have a number of favorable properties over films deposited on a TiN substrate without the plasma treatment. These include a smoother film surface, regular arrangement of Cu grains, and markedly increased ( 111)-preferred orientation. The postdeposition thermal annealing enhanced the (111)-preferred orientation and decreased the resistivity of the as-deposited Cu films. A combined process including Ar plasma substrate treatment prior to Cu film deposition and postdeposition thermal annealing at an appropriate temperature in N-2 ambient is proposed in order to achieve low-resistivity and highly (111)-oriented Cu film deposition. In this way, Cu films with a resistivity of 1.90muOhm.cm and a Cu(111)/Cu(200) peak ratio of 7.08 were obtained.
Coherent control multiphoton processes in semiconductor saturable Bragg reflector with freezing phase algorithm
(2005-03-01)
Chen, MC
;
Huang, JY
;
Chen, LJ
;
光電工程學系
;
Department of Photonics
A freezing phase concept has been proposed for adaptive coherent control with a femtosecond pulse shaper. We applied the scheme to investigate multiphoton processes in InAs quantum dot saturable Bragg reflector (SBR). The optical transition of InAs quantum dots can be revealed in the spectral phase sensitivity plot of second harmonic signal. We also achieved a three-time increase in image contrast on regions with photoluminescent wavelength differing only 18 nm by using coherent control nonlinear optical microscopy. Our results suggest the new freezing phase scheme to be useful for various investigations which require fast and reliable complete-field characterization and coherent control on one setup.
Common acoustical-poles/zeros modeling for 3D sound processing
(2000)
Chen, MC
;
Hsieh, SF
;
電信工程研究所
;
Institute of Communications Engineering
HRTFs(Head Related Transfer Functions) are a set of transfer functions from different spatial locations to both ears. They constitute an important database in 3-D sound signal processing. However, such an enormous data set makes real-time implementations difficult. Inspired by the resonant characteristic of pinnae, we seek a common-pole/zero model to reduce this vast data set. A Shanks common-poles model is proposed to improve previous Prony work. Based on a linearized least-squares criterion, a novel approach using iterative prefiltering and recursive updating the common poles is proposed and outperforms previous works.
Comparative study of physical and electrical characteristics of F- and C-doped low-K CVD oxides
(2001)
Wu, ZC
;
Shiung, ZW
;
Chiang, CC
;
Wu, WH
;
Chen, MC
This work makes a comparative study of physical and electrical properties between two species of inorganic low-K CVD oxides, namely F-doped FSG (fluorinated silicate glass, K=3.5) and C-doped OSG (organosilicate glass, K=2.9). It is found that FSG has a higher thermal stability (>600degreesC) than OSG (500degreesC) based on the results of 30 min thermal anneal in N-2 ambient. The degradation of the low-K property in OSG is predominately due to the thermal decomposition of methyl (CH3) groups at temperatures above 500degreesC, which are incorporated to reduce the density and polarizability of OSG. For the Cu-gated oxide-sandwiched low-K dielectric MIS capacitors, Cu permeation was observed in both FSG and OSG after the MIS capacitors were subjected to bias-temperature stressing (BTS) at 250 and 150degreesC, respectively, with an effective applied field of 0.8 MV/cm. It appeared that Cu drifted more readily in OSG than in FSG presumably because OSG has a more porous and less dense structure than FSG. The Cu penetration can be efficiently mitigated by a thin nitride dielectric barrier layer.