Browsing by Author "Chen, MJ"

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A model for low-temperature operation of minority-carrier well-type guard rings in epitaxial CMOS structures
(1998-03-01)
Huang, CY
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Chen, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As temperature is lowered, behaviors of well-type guard rings in an epitaxial substrate are quite different from those at RT so that the previous formulation is unable to reflect these discrepancies precisely. This leads to a new escape-current model suitable for low-temperature applications. In addition to the structural parameters, the new model is also functions of other physical quantities such as temperature, high-level injection, surface recombination velocity at the high/low junction and minority-carrier transport parameters, which are also important at low temperature. (C) 1997 Elsevier Science Ltd.
A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells
(2002-07-01)
Cho, CYS
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Chen, MJ
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Lin, JH
;
Chen, CF
;
電子工程學系及電子研究所
Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I-D = I-o exp[q(V-GB - nV(SB))/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients.
A new quantitative model for weak inversion charge injection in MOSFET analog switches
(1996-02-01)
Gu, YB
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Chen, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a new model concerning the channel charges in weak inversion injected from a turn-off MOSFET into a holding capacitor, This portion of charge injection has recently been newly observed, showing a significant contribution to the switch-induced error voltage on the switched capacitor, Our model is derived at the critical point where the device is operated in the transition region between strong inversion and weak inversion, This point has been expressed explicitly as a function of the DC input voltage, the threshold voltage, and the fall time of the gate voltage, The ability of the model in accurately determining quantitatively the impact of the weak inversion charge injection on the error voltage has been extensively judged experimentally and by two-dimensional mixed-mode simulation for a wide variety of design parameters such as the channel width and length, the holding capacitance, the fail time of the gate voltage, and the DC input voltage. The assumptions utilized in the model development have also been validated.
A novel cross-coupled inter-poly-oxide capacitor for mixed-mode CMOS processes
(1999-07-01)
Chen, MJ
;
Hou, CS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The inter-poly-oxide (IPO) capacitor is one of the main elements in present mixed-mode CMOS process technologies, However, the phenomenon of poly depletion causes a significant change in the measured capacitance with applied voltage, This effect, expressed in terms of the voltage coefficient of capacitance (VCC), can seriously deteriorate analog precision. In this letter, a novel cross-coupled scheme is proposed for the IPO capacitors. The resulting VCC has a very low measured value of 2 ppm/V in a 0.35-mu m standard mixed-mode CMOS process, achieved without any unconventional approaches.
A novel self-aligned highly reliable sidewall split-gate flash memory
(2006-03-01)
Cho, CYS
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Chen, MJ
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Chen, CF
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Tuntasood, P
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Fan, DT
A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F-2 (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 105 confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250 degrees C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.
A physical model for hole direct tunneling current in P+ poly-gate PMOSFETs with ultrathin gate oxides
(2000-11-01)
Yang, KN
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Huang, HT
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Chang, MC
;
Chu, CM
;
Chen, YS
A model of the hole direct tunneling gate current accounting for heavy and light hole's subbands in the quantized inversion layer is built explicitly. This model comprises four key physical parameters: inversion layer charge density, hole impact frequency on SiO2/Si interface, WKB transmission probability, and reflection correction factor. With the effective hole mass m(oxh) = 0.5m(o) for parabolic dispersion relationship in the oxide, experimental reproduction without any parameter adjustment is consistently achieved in p(+) poly-gate pMOSFETs with 1.23, 1.85, and 2.16 nm gate oxide thicknesses. The proposed model can thereby serve as a promising characterization means of direct tunnel oxides. In particular, it is calculated that the secondary subbands and beyond, although occupying few holes, indeed contribute substantially to the direct tunneling conduction due to effective lo,vcr barrier heights, and are prevailing over the first subbands for reducing oxide field down below 1 MV/cm.
A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
(1998-08-01)
Chen, MJ
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Lee, HS
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Chen, JH
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Hou, CS
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Lin, CS
A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings, This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined.
A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation
(1997-04-01)
Chen, MJ
;
Ho, JS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems, This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three, A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established, Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations, The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold CMOS analog circuit simulation.
A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation
(1997-04-01)
Chen, MJ
;
Ho, JS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold CMOS analog circuits and systems, This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three, A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established, Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations, The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold CMOS analog circuit simulation.
A trap generation closed-form statistical model for intrinsic oxide breakdown
(2001-06-01)
Huang, HT
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Chen, MJ
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Su, CW
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Chen, JH
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Hou, CS
A trap generation statistical model with the trap sphere radius r as parameter has been newly formulated in closed-form for intrinsic breakdown of ultrathin oxides and, by incorporating the trap filling fraction p as the secondary parameter, can be practically useful in a manufacturing process. Experimental reproduction for different oxide thicknesses and areas has been achieved through the model. A certain criterion has readily been drawn from the model, with which the ultimate thickness limit for breakdown can be set.
Active circuit's under wire bonding I/O, pads in 0.13 mu m eight-level Cu metal, FSG low-K inter-metal dielectric CMOS technology(+)
(2001-10-01)
Chou, KY
;
Chen, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active circuits in terms of ring oscillator are moved to the place under the wire bonding pads in 0.13 mum fall eight-level copper metal complementary metal-oxide-semiconductor process with fluorinated silicate glass low-k inter-metal dielectric. The bond pad with the 12 K Angstrom thick aluminum metal film. as a bonding mechanical stress buffer layer is deposited on the topmost copper metal layer. No noticeable degradations in gate delay or cycle time of ring oscillator are detected in a variety of test structures subjected to bonding mechanical stress and thermal cycling stress. This indicates that the underlying process technology may be reliable and manufacturable in placing active circuits under the bonding pads and thereby the die area utility is recovered fully. More evidence is created from transmission fine pulsing experiments as well as capacitive-coupling experiments.
Active devices under CMOS I/O pads
(2002-12-01)
Chou, KY
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Chen, MJ
;
Liu, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductoir process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V-t2, I-t2) of ESD protection devices under various metal level stack structures, shows that i) I-t2 depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V-t2 increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and dc electrical stress by transmission line pulse, as well as ac electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads is independent of bonding pad metal level structures.
An extraction method to determine interconnect parasitic parameters
(1998-11-01)
Chao, CJ
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Wong, SC
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Chen, MJ
;
Liew, BK
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電子工程學系及電子研究所
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
An extraction method to determine interconnect parasitic parameters
(1998-11-01)
Chao, CJ
;
Wong, SC
;
Chen, MJ
;
Liew, BK
;
電子工程學系及電子研究所
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's
(1998-04-01)
Chen, MJ
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Huang, HT
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Hou, CS
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Yang, KN
;
電子工程學系及電子研究所
The drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT, Each of the three shows different dependencies on hack-gate bias, As a result, the hulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage, Additional experiment highlights the effect of the increased hulk dopant concentrations as in next-generation scaled MOSFET's on the bulk BTBT, This sets the hulk BTBT a significant constraint to the low-voltage. low-power, high-density circuits employing the back-gate reverse bias, In the work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation.
Back-gate forward bias method for low-voltage CMOS digital circuits
(1996-06-01)
Chen, MJ
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Ho, JS
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Huang, TH
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Yang, CH
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Jou, YN
The back-gate forward bias method suitable for present standard hulk CMOS processes has been promoted for low-voltage digital circuit application, A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the de voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed, Guidelines for ensuring proper implementation of tile method in a bulk CMOS process has been set up against latch-up, parasitic bipolar, impact ionization, and stand-by current, Following these guidelines, a cost-effective low-power, low-voltage, high-density mixed-mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.
Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal-oxide-semiconductor transistors
(2006-02-06)
Lu, MP
;
Lee, WC
;
Chen, MJ
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Low-frequency noise measurement in process tensile-strained n-channel metal-oxide-semiconductor field-effect transistors yields the density of the interface states, exhibiting a decreasing trend while decreasing the channel width. This finding corroborates the group of P-b centers caused by the lattice mismatch at (100) Si-SiO2 interface as the origin of the underlying interface states. The inverse narrow width effect appears to be insignificant, substantially confirming the validity of the noise measurement. The present noise experiment therefore points to the enhancement of the tensile strain in the presence of channel narrowing, which in turn reduces the lattice mismatch.
Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs
(2001-06-01)
Yang, KN
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Huang, HT
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Chen, MJ
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Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of electron from n(+) polysilicon to underlying n-type drain extension in off-state n-channel MOSFET's having ultrathin gate oxide thicknesses (1.4-2.4 mm), It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT), and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field fox at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates fox to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension, Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
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Wong, SC
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Hsu, CJ
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Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.