Browsing by Author "Chen, Mei-Wei"

Now showing 1 - 2 of 2

A DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE
(2013-01-01)
Chen, Mei-Wei
;
Chang, Ming-Hung
;
Wu, Pei-Chen
;
Kuo, Yi-Ping
;
Yang, Chun-Lin
In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicitpulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to superthreshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781 ps, a setup time of 610ps, and a power dissipation of 2.3 mu W when the input voltage is OAV.
Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions
(2011)
Chang, Ming-Hung
;
Hsieh, Chung-Ying
;
Chen, Mei-Wei
;
Hwang, Wei
;
電子工程學系及電子研究所
The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1 similar to 1V and full temperature -50 similar to 125 degrees C range into account. The simulation results are using UMC 90-nm, PTM 65-, 45-and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45-and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.