Browsing by Author "Chen, Meng-Ling"

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On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer
(2012-01-01)
Hsu, Hsin-Wu
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Chen, Meng-Ling
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Chen, Hung-Ming
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Li, Hung-Chun
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Chen, Shi-Hao
Due to the advantage of flip-chip design in power distribution but controversial peripheral 10 placement in lower design cost, redistribution layer (RDL) is usually used for such interconnection. Sometimes RDL is so congested that the capacity for routing is insufficient. Routing therefore cannot be completed within a single layer even for manual routing. Although [2] proposed a routing algorithm that uses two layers of RDLs, but in practice the required routing area is a little more than one layer. We overcome this problem by adopting the concept of pseudo single-layer. With the heuristics for routing on mapped channels and observations on staggered pins to relieve vertical constraints, the area of 2-layer routing can be minimized and the routability is 100%. Comparisons of routing results between manual design, the commercial tool, and the proposed method are presented. We have shown the effectiveness on a real industrial case: it originally required fully manual design, the proposed method can finish RDL routing automatically and effectively.
Routability-Driven Bump Assignment for Chip-Package Co-Design
(2014-01-01)
Chen, Meng-Ling
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Tsai, Tu-Hsiung
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Chen, Hung-Ming
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Chen, Shi-Hao
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電子工程學系及電子研究所
In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.