Browsing by Author "Chen, Min-Chiao"

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A 3-10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits
(2009-11-01)
Wu, Chung-Yu
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Lo, Yi-Kai
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Chen, Min-Chiao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a g(m)-boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss (S(11)) and output return loss (S(22)) are less than -8.3 dB and -9 dB, respectively. The measured power gain (S(21)) is 11 +/- 1.5 dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm x 0.73 mm.
A 3.1 similar to 10.6 GHz CMOS direct-conversion receiver for UWB applications
(2006)
Wu, Chung-Yu
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Lo, Yi-Kai
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Chen, Min-Chiao
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 3.1 similar to 10.6 GHz fully integrated low-power CMOS direct-conversion receiver for ultra-wideband (UWB) applications is proposed and analyzed. The proposed receiver consists of a wideband low-noise amplifier (WLNA), quadrature down-conversion mixers, output I/Q buffers and a carrier generator. This chip was designed in 0.13-um CMOS technology. According to the simulation results, the proposed receiver has noise figure (NF) of 4.1 similar to 7.1 dB, receiver voltage gain of 22 dB, and input-referred 1-dB compression point (P-1dB) of -22 similar to-26 dBm and third-order intercept point (IIP3) of -12 similar to-16 dBm. It consumes 38.4 mW from 1.2 V power supply.
A CMOS Up-Conversion Mixer with Wide IF Bandwidth for 60-GHz Applications
(2009)
Chen, Min-Chiao
;
Chen, Huan-Sheng
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
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交大名義發表
In this paper, a direct up-conversion mixer with wide intermediate frequency (IF) bandwidth is designed and fabricated for 60-GHz applications. The up-converted differential signal is transformed to single-ended signal through an on-chip balun. In addition, an injection-locked frequency tripler is integrated for local oscillator signal generation. The measured results shows the maximum conversion gain of -5.6 dB, the input-referred JAB compression point (IP1dB) of -14 dBm, the third-order intercept point (IIP3) of -4 dBm, and 3-dB IF bandwidth of 3.5 GHz. The proposed up-conversion mixer is fabricated using 0.13-mu m standard CMOS technology, and it draws only 2.25 mA from 1.2-V supply.
A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-mu m CMOS for V-Band Applications
(2009-07-01)
Wu, Chung-Yu
;
Chen, Min-Chiao
;
Lo, Yi-Kai
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the V-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-mu m CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are -85.2 and -90.9 dBc/Hz, respectively. The reference spur level of -40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance V-band applications.
An integrated 60-GHz front-end receiver with a frequency tripler using 0.13-mu m CMOS technology
(2007)
Chen, Po-Hung
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Chen, Min-Chiao
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-mu m CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2-V power supply.
An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications
(2010-06-01)
Chen, Po-Hung
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Chen, Min-Chiao
;
Ko, Chun-Lin
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Wu, Chung-Yu
;
電子工程學系及電子研究所
A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SET) for V-band applications is designed, fabricated and measured using 0.13-mu m CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SET. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm x 0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.
Design and analysis of CMOS subharmonic injection-locked frequency triplers
(2008-08-01)
Chen, Min-Chiao
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
K- and V-band CMOS differential subharmonic injection-locked frequency triplers (ILFTs) are proposed, analyzed, and designed. Based on the proposed ILFT structure, models for the injection-locking range and the output phase noise are developed. A K-band ILFT is designed and fabricated using 0.18-mu m standard CMOS technology. The measured injection-locking range is 1092 MHz with a dc power consumption of 0.45 mW and an input injection power of 4 dBm. The harmonic rejection ratios are 22.65, 30.58, 29.29, 40.35 dBc for the first, second, fourth, and fifth harmonics, respectively. The total injection-locking range of the K-band ILFT can achieve 3915 MHz when the varactors are used and the dc power consumption is increased to 2.95 mW. A V-band ILFT is also designed. and fabricated using 0.13-mu m standard CMOS technology. The measured injection-locking range is 1422 MHz with 1.86-mW dc power consumption and 6-dBm input injection power. The injection-locking range of the proposed ILFT is similar to the tuning range of a conventional varactor-tuned bulk-CMOS voltage-controlled oscillator (WO). Moreover, the proposed ILFT has a greater output power and a lower dc power consumption level than a VCO. As a result, it is feasible to use the proposed ILFT in low-power millimeter-wave synthesizers.