Browsing by Author "Chen, Ming-Jer"

Now showing 1 - 20 of 36

A constant-mobility method to enable MOSFET series-resistance extraction
(2007-12-01)
Lin, Da-Wen
;
Cheng, Ming-Lung
;
Wang, Shyh-Wei
;
Wu, Chung-Cheng
;
Chen, Ming-Jer
A new method of extracting the MOSFET series resistance R-sd is proposed. This method requires only simple dc measurements on a single test device. Experimental demonstration is presented, without requiring quantities such as gate-oxide thickness, physical gate length, or effective channel length. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. It is this unique property which, makes the proposed method suitable for short-channel devices.
A Method of Extracting Metal-Gate High-k Material Parameters Featuring Electron Gate Tunneling Current Transition
(2011-04-01)
Hsu, Chih-Yu
;
Chang, Hua-Gang
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For metal-gate high-k dielectrics, there is a transition region in the electron gate tunneling current I(g), as characterized by a plot of dlnI(g)/dV(g) versus V(g). In this paper, we systematically construct a new fitting over the region, which can accurately determine material parameters, including metal work function, high-k electron affinity, and tunneling effective masses of electrons. First of all, a calculation of gate current due to electron direct tunneling and/or Fowler-Nordheim tunneling from an inversion layer is performed, yielding the guidelines of the fitting. Experimental samples are presented with n-channel metal-oxide-semiconductor field-effect transistors having low effective oxide thickness (1.4 nm) TaC/HfSiON/SiON gate stacks. Underlying material parameters are extracted accordingly and remain valid for higher temperature and gate voltage. We also demonstrate that a conventional method without a dlnI(g)/dV(g) fitting might lead to erroneous results. Thus, the dlnI(g)/dV(g) fitting is crucial to metal-gate high-k material parameter assessment.
A millisecond-anneal-assisted selective fully silicided (FUSI) gate process
(2008-09-01)
Lin, Da-Wen
;
Wang, Maureen
;
Cheng, Ming-Lung
;
Sheu, Yi-Ming
;
Tarng, Bennet
We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (NISA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for PMOSFETs with the feature size down to 30 run. A 20% improvement in FUSI-gated PMOSFET I-on-I-off is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.
A Model for Neutral Defect Limited Electron Mobility in Strained-Silicon Inversion Layers
(2017-03-01)
Hsieh, Shang-Hsun
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On the strained silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), we show how to derive a formalism dealing with the scattering of a 2-D electron by a neutral defect. The corresponding neutral defect limited inversion-layer electron mobility, mu(n), is calculated in the momentum relaxation time approximation. The calculated results lead to a new analytical model: mu(n) = cN(n)(-1) where N-n is the neutral defect density per unit area and c is the coefficient independent of the inversion-layer density, the strain, and the temperature. The validity and applicability of the model are confirmed by citing three independent experiments on strained silicon MOSFETs undergoing different implantation sources and different annealing budgets. Importantly, this paper clarifies for the first time that strain will not change neutral defect limited mobility unless changing the neutral defect density. This reasonably explains the two experimental observations during implantation and annealing: 1) the implantation-induced strain relaxation in strained sample does not occur and 2) the neutral defect density is much higher in strained sample than in unstrained sample.
A New Microscopic Formalism for the Electron Scattering by Remote "Paired" Dipoles in HKMG MOSFETs
(2016)
Hsieh, Shang-Hsun
;
Hung, Jo-Chun
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We devise a new microscopic formalism for the remote dipole scattering (RDS) limited relaxation time in the inversion layers of HKMG MOSFETs. This formalism can apply to two different dipole configurations: (i) a "one dipole" configuration and (ii) a "paired dipoles" configuration. We find that when fitting the inversion-layer effective electron mobility measured from the industry-level hafnium-based metal gate MOSFETs, the former configuration yields a large value of the HK/IL interface dipole density of around 1015 cm(-2), accompanied by a large threshold voltage shift Delta V-th_dipole of 12 V. These values are comparable with those of the existing Monte Carlo simulation. More importantly, in case of the latter configuration (paired dipoles) plus the experimentally determined fixed charges, the corresponding values can be significantly reduced to 10(14) cm(-2) and 2 V, which are quite close to the experimental estimations in the literature.
A Novel Method of MOSFET Series Resistance Extraction Featuring Constant Mobility Criteria and Mobility Universality
(2010-04-01)
Lin, Da-Wen
;
Cheng, Ming-Lung
;
Wang, Shyh-Wei
;
Wu, Chung-Cheng
;
Chen, Ming-Jer
A method of MOSFET series resistance extraction is established in this paper. The core of this method relies on the constant mobility criteria, while for different gate lengths, it preserves the shape of universal mobility curves in the high-vertical-field regime. Consequently, the series resistance of a MOSFET can be extracted in an analytical and self-consistent manner, achieved without the knowledge of the gate oxide thickness, channel length, channel doping, or channel stress. Reasonable values of extracted series resistance are demonstrated in a wide range of gate length. Technology computer-aided design simulation further corroborates the validity of the proposed method, particularly for devices with heavily doped source/drain extensions. The constant mobility criteria with respect to the bulk charge linearization coefficient are also verified.
A parabolic potential barrier-oriented compact model for the kappa T-B layer's width in nano-MOSFETs
(2008-05-01)
Chen, Ming-Jer
;
Lu, Li-Fang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On the basis of a parabolic potential profile around the source-channel junction barrier of nanoscale MOSFETs, a new compact model is physically derived, which links the width of thermal energy kappa T-B layer (a critical zone in the context of the backscattering theory) to the geometrical and bias parameters of the devices. The proposed model is supported by experimental data and by a critical analysis of various simulation works presented in the literature. The only fitting parameter remains constant in a wide range of channel length (10-65 nm), gate voltage (0.4-1.2 V), drain voltage (0.2-1.2 V), and temperature (100 K-500 K). The confusing temperature-dependent issues in the open literature are straightforwardly clarified.
A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs
(2014-07-01)
Chen, Ming-Jer
;
Tu, Kong-Chiang
;
Wang, Huan-Hsiung
;
Chen, Chuan-Li
;
Lai, Shiou-Yi
Trapping-detrapping of a single electron via an individual trap in metal-oxide-semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. Recent 3-D technology computer-aided design (TCAD) simulations, on an individual MOSFET, revealed that with the position of the trap as a random variable, resulting random telegraph signals relative magnitude Delta I-d/I-d in the subthreshold current at low drain voltage can have two distinct distributions: a headed one for a percolation-free channel and a tail one for a percolative channel. The latter may be effectively treated by a literature formula: (Delta I-d/I-d) = (I-loc/I-d)(2), where I-loc is the local current around the trap. In this paper, we show how to make this formula practically useful. First, we conduct 3-D TCAD simulations on a 35 x 35-nm(2) channel to provide Delta I-d/I-d for a few positions of the trap. This leads to a new statistical model in closed form, which can reproduce headed distributions. Straightforwardly, key criteria are drawn from the model, which can act as guidelines for the adequate use of the I-loc/I-d formula. Extension to threshold voltage shift counterparts, from subthreshold through transition to inversion, is successfully achieved. Importantly, use of the model may overcome the drawbacks of the statistical experiment or simulation in the field.
An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow
(2010-09-01)
Lin, Da-Wen
;
Chen, Chien-Liang
;
Chen, Ming-Jer
;
Wu, Chung-Cheng
;
電子工程學系及電子研究所
This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using self-aligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.
Criteria for Plasmon-Enhanced Electron Drag in Si Metal-Oxide-Semiconductor Devices
(2015-03-01)
Chen, Ming-Jer
;
Hsieh, Shang-Hsun
;
Liao, Yu-Chiao
;
Chen, Chuan-Li
;
Tsai, Ming-Fu
Plasmons in the highly doped source and drain regions of silicon field-effect transistors can strongly drag channel electrons via long-range collective Coulomb interactions and cause deteriorations in overall device performances. To examine such interactions, two different methods have been published: 1) sophisticated device simulations and 2) carefully calibrated experiments. To provide a more transparent understanding, we propose a third method in terms of two criteria: 1) one for the occurrence of the plasmon resonance and 2) the other for the strength of the plasmons. The former is determined based on our published dragged mobility data due to the interface plasmons and the bulk plasmons in gate. The latter makes use of our more recently experimentally extracted potential fluctuations due to plasmons in crystalline silicon. The effects of the temperature on the criteria are considered. It is a straightforward task to confirm that for a channel density larger than approximately 5 x 10(12) cm(-2), the source and drain plasmons act as key limiters in silicon device scaling. Therefore, the underlying device physics, modeling, simulations, experimental analyses, and data interpretation may be inaccurate if the limiting factors are not incorporated.
Distinguishing Between STI Stress and Delta Width in Gate Direct Tunneling Current of Narrow n-MOSFETs
(2009-05-01)
Hsieh, Chen-Yu
;
Lin, Yi-Tang
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Direct tunneling current across a 1.27-nm-thick gate oxide of n-MOSFETs under STI compressive stress is measured in a wide range of the drawn gate width W (= 0.11, 0.24, 0.6, 1.0 and 10 mu m). The apparent gate current per unit width exhibits an increasing trend with decreasing W. In this narrowing direction, two fundamentally different effects are encountered: one of the delta width (Delta W) near the STI edge, and the other of the enhanced STI stress in the channel. To distinguish between the two effects, a new analytical width-dependent direct tunneling model is developed and applied. Reasonable agreement with data is achieved. The resulting delta width effect is found to dominate over the stress effect in narrow devices, while for the wide ones, they are comparable. The extracted Delta W (similar to 63 nm) and the underlying channel stress (with the uncertainties identified) straightforwardly produce a good fitting of the drain current variation counterpart. Specifically, it is justified that the delta width and STI stress are cooperative in constituting gate current variation, but both have opposite effects on the drain current one.
Effect of Strained k . p Deformation Potentials on Hole Inversion-Layer Mobility
(2013-04-01)
Chen, Ming-Jer
;
Lee, Chien-Chih
;
Chen, Wan-Li
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In the literature dedicated to strained p-type metal-oxide-semiconductor field-effect transistor inversion-layer mobility calculation via a k . p valence-band structure, three key strain-related material parameters, namely, the Bir-Pikus deformation potentials a(upsilon), b, and d, were widespread in magnitude. To improve such large discrepancies, in this paper, we conduct sophisticated calculations on < 110 >/(001) and < 110 >/(110) hole inversion-layer mobility for gigapascal-level uniaxial stresses along each of three crystallographic directions. The screening effect on surface roughness scattering is taken into account. We find that, to affect the calculated hole mobility enhancement, a(upsilon) is weak, b is moderate, and d is strong, particularly for the uniaxial compressive stress along the < 110 > direction. This provides experimental guidelines for an optimal determination of the primary factor, i.e., d, and the secondary factor, i.e., b, with the commonly used values for a(upsilon). The result remains valid for varying surface roughness parameters and models and is supported by recent first-principles and tight-binding calculations. Thus, the strained k . p valence-band structure with the optimized deformation potentials can ensure the accuracy of the calculated transport properties of 2-D hole gas under stress.
Effect of uniaxial strain on anisotropic diffusion in silicon
(2006-10-16)
Chen, Ming-Jer
;
Sheu, Yi-Ming
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A physical model is directly extended from the thermodynamic framework to deal with anisotropic diffusion in uniaxially stressed silicon. With the anisotropy of the uniaxial strain induced activation energy as input, two fundamental material parameters, the activation volume and the migration strain anisotropy, can be quantitatively determined. When applied to boron, a process- device coupled simulation is performed on a p-type metal-oxide-semiconductor field-effect transistor undergoing uniaxial stress in a manufacturing process. The resulting material parameters have been found to be in satisfactory agreement with values presented in the literature. (c) 2006 American Institute of Physics.
Electrical measurement of local stress and lateral diffusion near Source/Drain extension corner of uniaxially stressed n-MOSFETs
(2008-03-01)
Hsieh, Chen-Yu
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
-On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.
Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs
(2009-08-01)
Hsu, Chih-Yu
;
Lee, Chien-Chih
;
Lin, Yi-Tang
;
Hsieh, Chen-Yu
;
Chen, Ming-Jer
On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.
Error-Free Matthiessen's Rule in the MOSFET Universal Mobility Region
(2013-02-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
Huang, Yi-Hui
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Through the experimentally validated inversion-layer mobility simulation, we devise an error-free version of Matthiessen's rule for a single-gate n-channel bulk MOSFET in the universal mobility region. The core of the new rule lies in a semi-empirical model, which explicitly expresses the errors due to the conventional use of Matthiessen's rule as a function of both the lowest subband population and the relative strength of individual mobility components. The model holds under practical conditions (with temperatures up to 400 K) and in a broad range of substrate doping concentrations (10(14) to 10(18) cm(-3)). To make the error-free proposal more general, we elaborate on several issues, including strain, impurity Coulomb scattering, and remote scattering. The thin-film case can be treated accordingly.
Evidence for a Very Small Tunneling Effective Mass (0.03m(0)) in MOSFET High-k (HfSiON) Gate Dielectrics
(2012-04-01)
Chen, Ming-Jer
;
Hsu, Chih-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have recently conducted experimental and modeling tasks on TaC/HfSiON/SiON n-type MOSFETs, leading to an effective mass of 0.03m(0) for 2-D electrons tunneling in high-k HfSiON dielectrics. In this letter, we present extra evidence obtained from complementary MOSFETs undergoing the same TaC/HfSiON/SiON processing, which shows that such a very small tunneling effective mass is existent not only for 3-D electrons but also for 2-D holes. This new finding is very important because it can substantially enhance the current understanding of gate tunneling leakage suppression in metal-gate high-k MOSFETs.
Evidence for the Fourfold-Valley Confinement Electron Piezo-Effective-Mass Coefficient in Inversion Layers of < 110 > Uniaxial-Tensile-Strained (001) nMOSFETs
(2012-06-01)
Chen, Ming-Jer
;
Lee, Wei-Han
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have recently experimentally extracted the piezo-effective-mass coefficients of 2-D electrons via the gate tunneling current of (001) n-channel metal-oxide-semiconductor field-effect transistors under < 110 > uniaxial compressive stress. The results pointed to the existence of a piezo-effective-mass coefficient around the fourfold conduction-band valley in the out-of-plane (quantum confinement) direction. To strengthen this further, here, we provide extra evidence. First, explicit guidelines are drawn to distinguish all the piezo-effective-mass coefficients. Then, a self-consistent strain quantum simulation is executed to fit literature data of both the mobility enhancement and gate current suppression in the uniaxial tensile stress situation. It is found that neglecting the fourfold-valley out-of-plane piezo-effective-mass coefficient, as in existing band structure calculations, only leads to a poor fitting.
Exposure to Mono-n-Butyl Phthalate in Women with Endometriosis and Its Association with the Biological Effects on Human Granulosa Cells
(2020-03-01)
Chou, Ya-Ching
;
Chen, Yu-Chun
;
Chen, Ming-Jer
;
Chang, Ching-Wen
;
Lai, Guan-Lin
To study the association between urinary phthalate metabolite levels, endometriosis, and their effects on human granulosa cells, we recruited patients who underwent laparoscopy to confirm endometriosis (n = 123) and control patients (n = 78). Liquid chromatography-tandem mass spectrometry was used to measure the following five urinary phthalate metabolites: mono-n-butyl phthalate (MnBP), mono(2-ethylhexyl) phthalate, monobenzyl phthalate, mono(2-ethyl-5-oxo-hexyl) phthalate, and mono(2-ethyl-5-hydroxyhexyl) phthalate. Urinary MnBP levels were higher in patients with endometriosis than in controls after multivariable logistic regression including the number of deliveries, body mass index, and use of medicine as covariables. MnBP correlates with other phthalate metabolites. Previous studies found that endometriosis was a detrimental condition for granulosa cells. In our study, we observed whether MnBP affected granulosa cells. MnBP treatment altered the gene expression of BIRC5, BUB1B, CDC20, cyclin B1, IL-1 beta, TNF-alpha, inhibin-B, StAR, and P450ssc and attenuated the ratio of the mitochondrial membrane potential in human granulosa cells. Moreover, MnBP decreased the expression of the anti-Mullerian hormone. These findings suggest that MnBP concentration is associated with endometriosis and may affect the health and steroidogenesis of human granulosa cells.
Gate Direct Tunneling Current in Uniaxially Compressive Strained nMOSFETs: A Sensitive Measure of Electron Piezo Effective Mass
(2011-01-01)
Lee, Wei-Han
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Currently, both the band-structure calculation and the mobility measurement are used to assess the electron piezo-effective-mass coefficients in strained nMOSFETs. In this paper, we present a new experimental method through a fitting of the strain-altered electron gate direct tunneling current. The core of this method lies in the sensitivity of the direct tunneling to the position of the subband level in the presence of the electron piezo-effective-mass coefficients. First, a correction-coefficient generating expression is systematically constructed to compensate for the error in the subband levels due to the use of a triangular potential approximation. Then, with the known deformation potential constants and uniaxially compressive stress in the channel as inputs, a strain quantum simulator is carried out. The resulting gate direct tunneling current is used to fit experimental data, thus leading to the values of the piezo-effective-mass coefficients associated with the twofold and fourfold valleys. The comparison of the extracted piezo-effective-mass coefficients to those published in the literature is made.