<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

Browsing by Author "Chen, P. -C."

Now showing 1 - 1 of 1
  • Thumbnail Image
    Item type:Item,
    High Performance Silicon N-channel Gate-All-Around Junctionless Field Effect Transistors by Strain Technology
    (2016)
    Sung, P. -J.
    ;
    Cho, T. -C.
    ;
    Chen, P. -C.
    ;
    Hou, F. -J.
    ;
    Lai, C. -H
    In this paper, strain effects on silicon n-channel gate-allaround (GAA) jucntionless field effect transistor (JLFET) are studied. By using tensile strain SiN layer, drive currents of the JLFETs show enhancement of up to 42%. The high performance strained JLFETs exhibit superior gate control (I-on/I-off > 10(9)) and ideal S.S. (65 mV/dec.) as a channel width scales down to 20 nm. Drive currents and leakage currents are improved simultaneously after inducing strain technology.