Browsing by Author "Chen, P. H."

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GaN-Based Light-Emitting-Diode With a p-InGaN Layer
(2014-03-01)
Chen, P. H.
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Kuo, Cheng-Huang
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Lai, W. C.
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Chen, Yu An
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Chang, L. C.
GaN-based LEDs with a p-InGaN layer was proposed and fabricated. By inserting the 50-nm-thick p-In0.01Ga0.99N layer, it was found that we could reduce the 20 mA forward voltage from 3.34 to 2.99 V. It was found the inserted p-InGaN layer could also reduce the efficiency droop from 36.7% to 23.8%.
Low operation voltage of GaN-based LEDs with Al-doped ZnO upper contact directly on p-type GaN without insert layer
(2015-07-01)
Chen, P. H.
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Chen, Yu An
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Chang, L. C.
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Lai, W. C.
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Kuo, Cheng Huang
Al-doped ZnO (AZO) film was evaporated on double-side polished sapphire, p-GaN layers, n(+)-InGaN-GaN short-period superlattice (SPS) structures, and GaN-based light-emitting diodes (LEDs) by e-beam. The AZO film on the p-GaN layer after thermal annealing exhibited an extremely high transparency (98% at 450 nm) and a small specific contact resistance of 2.19 x 10(-2) Omega cm(2), which was almost the same as that of as-deposited AZO on n(+)-SPS structure. With 20 mA injection current, the forward voltages were 3.30 and 3.27 V, whereas the output powers were 4.32 and 4.07 mW for the LED with AZO on insert n(+)-SPS upper contact and the LED with AZO on p-GaN upper contact (without insert layer), respectively. The small specific contact resistance and low operation voltage of LED with AZO on p-GaN upper contact was achieved by rapid thermal annealing (RTA) process. (C) 2015 Elsevier Ltd. All rights reserved.
Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_Line
(2019-01-01)
He, C. Y.
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Tang, K. H.
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Chen, T. S.
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Chang, K. Y.
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Lin, C. H.
A 0.45 V 28-nm 32 -Kb SRAM with multi-powersupply low-power circuits, such as a cross-point 5T with built-in Y_line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.