Browsing by Author "Chen, P. S."

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Highly Scalable Hafnium Oxide Memory with Improvements of Resistive Distribution and Read Disturb Immunity
(2009)
Chen, Y. S.
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Lee, H. Y.
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Chen, P. S.
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Gu, P. Y.
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Chen, C. W.
A 30x30 nm(2) HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 10(6) cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (R-HIGH) and low resistance (R-LOW) are proposed for the array to ensure a good operation window. A thin A1O(x) buffer layer under the HfOx layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program(PGM)/erase(ERS) disturb immunity.
Ni silicide formation on epitaxial Si(1-y)C(y)/(001) layers
(2010-10-01)
Lee, S. W.
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Huang, S. H.
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Cheng, S. L.
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Chen, P. S.
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Wu, W. W.
The formation of Ni silicides on Si(1 - y)C(y) (y=0.01 and 0.018) epilayers grown on Si(001) has been investigated. The presence of C atoms was found to significantly retard the growth kinetics of NiSi and enhances the thermal stability of thin NiSi films. For Ni(11 nm)/Si(0.982)C(0.018) samples, the process window of NiSi was shifted and extended to 450-700 degrees C. Moreover, there was an additional strain introduced into the Si(1 - y)C(y) epilayers during Ni silicidation. This work shows the potential of Ni silicidation on Si(1y)C(y) for device applications. (C) 2010 Elsevier B.V. All rights reserved.
Ni silicide formation on epitaxial Si1-yCy/(001) layers
(2010-10-01)
Lee, S. W.
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Huang, S. H.
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Cheng, S. L.
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Chen, P. S.
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Wu, W. W.
The formation of Ni silicides on Si1 - yCy (y=0.01 and 0.018) epilayers grown on Si(001) has been investigated. The presence of C atoms was found to significantly retard the growth kinetics of NiSi and enhances the thermal stability of thin NiSi films. For Ni(11 nm)/Si0.982C0.018 samples, the process window of NiSi was shifted and extended to 450-700 degrees C. Moreover, there was an additional strain introduced into the Si1 - yCy epilayers during Ni silicidation. This work shows the potential of Ni silicidation on Si1yCy for device applications. (C) 2010 Elsevier B.V. All rights reserved.
Structural Design, Process, and Reliability of a Wafer-Level 3D Integration Scheme with Cu TSVs Based on Micro-bump/Adhesive Hybrid Wafer Bonding
(2012)
Ko, C. T.
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Hsiao, Z. C.
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Chang, Y. J.
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Chen, P. S.
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Huang, J. H.
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5 mu m TSV, 10 mu m microbump, 20 mu m pitch, 40 mu m thin wafer, and 250 degrees C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.