Browsing by Author "Chen, Pin-Chun"

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Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
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Liu, Jen-Chieh
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Shen, Yu-Lin
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Chou, Teyuh
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Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Interchangeable Hebbian and Anti-Hebbian STDP Applied to Supervised Learning in Spiking Neural Network
(2018-01-01)
Chang, Che-Chia
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Chen, Pin-Chun
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Hudec, Boris
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Liu, Po-Tsun
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Hou, Tuo-Hung
This work provides a complete framework, including device, architecture, and algorithm, for implementing bio-inspired supervised spiking neural networks (SNNs) on hardware. An analog synapse with atypical dual bipolar resistive-switching (D-BRS) modes demonstrates interchangeable Hebbian spiking-timing-dependent plasticity (STDP) and anti-Hebbian STDP, and it is capable of implementing supervised ReSuMe SNNs in crossbar arrays. By using an "exchange" update scheme, accurate supervised learning (similar to 96% for MNIST) is achieved in a compact network.
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse
(2018-03-01)
Chang, Chih-Cheng
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Chen, Pin-Chun
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Chou, Teyuh
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Wang, I-Ting
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Hudec, Boris
Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses, because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms. New insights on engineering activation functions and a threshold weight update scheme effectively suppress the undesirable training noise induced by inaccurate weight update. We successfully trained a two-layer perceptron network online and improved the classification accuracy of MNIST handwritten digit data set to 87.8%/94.8% by using 6-/8-b analog synapses, respectively, with extremely high asymmetric nonlinearity.