Browsing by Author "Chen, Po-Ting"

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Characterization of the Channel-Shortening Effect on P-Type Poly-Si TFTs
(2010-03-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Po-Ting
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光電工程學系
;
顯示科技研究所
The phenomenon of channel shortening for p-type poly-Si thin-film transistors (TFTs) after stress is studied in this paper. Increased mobility, shifted threshold voltage V(TH), and reduced leakage current for the stressed device are observed. In addition, the capacitance-voltage (C-V) behavior for the stressed device exhibits the anomalous increase for the measuring gate voltage in the OFF region. A model illustrating how the trap electron mechanism would occur is provided. Furthermore, the degradation behavior of the p-type poly-Si TFT under gate ac stress in the OFF region is also studied. Similar degradation behaviors are observed for the gate-ac-stressed TFT for both of their I-V and C-V characteristics. A distributed device circuit model is proposed, and based on this model, it is proposed that the main voltage drop during gate ac stress in the OFF region could occur at the source and drain junction, which may, in turn, degrade the device. A gated p-i-n device under the same process condition is then adopted and dc stressed to verify the proposed mechanism. The similarity between the capacitance curves for the ac-stressed TFT and the dc-stressed gated p-i-n device proves the validity of the proposed mechanism.
Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region
(2009-03-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
;
Chen, Po-Ting
;
光電工程學系
;
顯示科技研究所
This letter reports the study of the reliability behavior of poly-Si thin-film transistors (TFTs) with the pulsed gate voltage lower than the threshold voltage. First, the equivalent circuit model for poly-Si TFT is proposed. Considering the voltage drop for each element in the circuit model during the OFF-region gate dynamic stress, it is proposed that the main voltage drop occurs at the source and drain junctions, which could in turn degrade the device during stress. Based on this assumption, the gated p-i-n device fabricated on the same glass with the identical process conditions is stressed and analyzed. The similarity between the capacitance curves of the TFTs and gated p-i-n devices after stress proves that the main reason for degradation of poly-Si TFTs under gate OFF region ac stress is the large Voltage drop across the source and drain junctions.
Generalized Hot-Carrier Degradation and Its Mechanism in Poly-Si TFTs Under DC/AC Operations
(2011-03-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Po-Ting
;
Lin, Chih-Jung
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光電工程學系
In the previous report, we had reported the mechanism for the degradation of poly-Si TFTs under OFF region gate ac operation with the source and drain electrodes grounded. In this paper, the study is extended to the degradation of the devices under various ac and dc operation conditions. It is discovered that, though these stress conditions are different, the corresponding degradation behaviors in their I-V and C-V curves all resemble the degradation behavior of the device under dc hot-carrier stress. Two important factors, namely, the electric field across the junction and the number of carriers flowing through the junction, are taken into discussion in this paper and comparison of these stress conditions. It is then categorized that these operation conditions can be described as the "generalized hot-carrier effect," since the degradation is found to occur near the junctions by the energized carriers, just as that under dc hot-carrier stress. The qualitative comparison of the electric field and carrier flow through the junction for the four stress conditions as well as the difference in the degradation mechanism between MOSFETS and poly-Si TFTs are also provided.
Job-Level Proof Number Search
(2013-03-01)
Wu, I. -Chen
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Lin, Hung-Hsuan
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Sun, Der-Johng
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Kao, Kuo-Yuan
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Lin, Ping-Hung
This paper introduces an approach, called generic job-level search, to leverage the game-playing programs which are already written and encapsulated as jobs. Such an approach is well suited to a distributed computing environment, since these jobs are allowed to be run by remote processors independently. In this paper, we present and focus on a job-level proof number search (JL-PNS), a kind of generic job-level search for solving computer game search problems, and apply JL-PNS to solving automatically several Connect6 positions, including some difficult openings. This paper also proposes a method of postponed sibling generation to generate nodes smoothly, and some policies, such as virtual win, virtual loss, virtual equivalence, flagging, or hybrids of the above, to expand the nodes. Our experiment compared these policies, and the results showed that the virtual-equivalence policy, together with flagging, performed the best against other policies. In addition, the results also showed that the speedups for solving these positions are 8.58 on average on 16 cores.