Browsing by Author "Chen, SG"

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A CORDIC processor with efficient table-lookup schemes for rotations & on-line scale factor compensations
(2005)
Chih, JC
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Chen, KL
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we improve our previous efficient CORDIC processor design. The improvements consist of two parts: (1) an improved table-lookup rotation scheme with a smaller table than before, and (2) a new efficient on-line table-lookup scheme for scale-factor computations and compensations which is better than the previous non-online design. Combining the improvements with the original efficient rotation angle recoding algorithm and leading-one (or zero) bit detection (for skipping redundant rotations), we obtain a lowiteration and low-complexity COREDC processor architecture. The design is more efficient than the current designs, especially in the iteration count. Simulation shows that for n-bit results, about only n/4 iterations are required. We also designed a 16-bit CORDIC processor based on 0.25 mu m UMC process. Its averaged iteration count is only 4.4 including rotation and scale factor compensations, with a total gate count of 5742 and a maximum operating frequency of 250MHz.
A fast CORDIC algorithm based on a novel angle recoding scheme
(2000)
Chih, JC
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Chen, SG
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a new CORDIC algorithm, which considerably reduces rotation number. It is achieved by combining several design techniques. Particularly, a new angle recoding scheme for table lookup is developed to speed up the convergence rate of the rotation angle. The required lookup table is small. Other design techniques used include: the leading-one bit detection, the variable-scale-factor compensation algorithm [6]. The number of the shift-and-add operations required in the compensation algorithm can be also further reduced by using the same residue recoding scheme. Simulations show that in aver;ige the new design needs only 3.5; iterations to generate results with 22-bit precision, which is much less than the existing designs (normally need 22 iterations). The new encoding scheme can be applied to other iterative convergence computation function such as division operation.
A low-complexity correlation algorithm
(2003)
Cheng, KF
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
For the consideration of low power, and fast code acquisition, four new low-complexity correlation algorithms are proposed in this work. Among them, the one derived by combing the differential coding scheme and a fast filtering algorithm has the lowest complexity. The new algorithm reduces the direct N addition operations to 5N/16. As a result, close to 70% reduction is obtained. When compared with the fast correlation algorithm based on the differential coding scheme, which costs N/2 addition operations, close to 40% reduction is obtained. The new algorithm can be further combined with the sub-expression sharing techniques for a much significant complexity reduction. The proposed design is best suited for DSP realization.
A new approach to the design of QMF banks
(1998)
Kao, MC
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
New L-2 objective functions for the design of quadrature-mirror-filter (QMF) banks are proposed. They are based on the derivative information of the reconstruction error. Simple and explicit matrix-form expressions for the proposed objective functions are derived. An efficient design method is proposed by incorporating a separability technique into the derived optimality conditions on prototype filters. The proposed method only needs to solve linear equations iteratively without nonlinear optimization. Design examples demonstrate that good low-delay QMF banks and linear-phase QMF banks can be obtained after a few iterations. Compared to the conventional approach, the new approach leads to QMF banks with larger stopband attenuation and smaller reconstruction errors.
A new efficient algorithm for singular value decomposition
(1999)
Chen, SG
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Chang, CC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The popular CORDIC-based SVDs suffer from the disadvantages of inherently sequential operations and requiring area-consuming barrel shifters. On the other hand, the basic-arithmetic SVD needs nasty division and square-root operations. To alleviate these problems, a new algorithm for SVD computation is proposed. Instead of using CORDIC algorithm, the new algorithm is based on multiplication-and-addition operations (without nasty division and square-root operations), combined with an approximate rotation and table lookup scheme, As a result, the new algorithm has a smaller computational complexity than those of the conventional SVD algorithms, in terms of number of addition operations. In realization, it also has a higher parallelism and smaller area than the conventional CORDIC-based SVD processors.
A new efficient LMS adaptive filtering algorithm
(1996-05-01)
Chen, SG
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Kao, YA
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Tsai, KY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new efficient LMS adaptive filtering algorithm is proposed, The algorithm has comparable performance to that of the direct-form LMS algorithm (DLMS), while costs N/2 - 1 fewer multiplications at the expense of N/2 + 5 more additions than the DLMS algorithm, where N is the number of filter taps, The new algorithm has one more parameter adaptation than the DLMS algorithm. Further, the algorithm was combined with sign LMS algorithm (SA), signed regressor algorithm (SRA) and zero forcing (ZFA) algorithm for more complexity reduction. Simulation results showed that the new combined algorithms converge as fast as the direct-form SA, SRA and ZFA algorithms, meanwhile still maintain comparable performances.
A new type of perfect-reconstruction QMF banks
(1997)
Chen, SG
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Kao, MC
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Chen, SP
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交大名義發表
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電子工程學系及電子研究所
A new type of perfect-reconstruction QMF system is proposed. The filter system is based on half-band filters so that it has lower complexity and group delay than the known QMF systems, with a comparable performance. It is shown that the new PR QMF system achieves zero phase distortion and zero amplitude distortion, in addition to producing aliase-free outputs. A filter optimization technique is also proposed for its prototype low pass filter. For realization, its polyphase architecture is derived, which has very simple structure.
A novel iterative design technique for linear-phase FIR half-band filters
(2000)
Kao, MC
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Chen, SG
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a novel iterative design scheme for generating linear-phase, half-band FIR filters with considerably reduced arithmetic operations and narrow transition bandwidth. Starting from a short half-band subfilter, preferably a multiplier-free one, the scheme can evolve this subfilter to a better composite half-band filter by using simple algebraic composition transformation iteratively. Compared to the existing design methods, the proposed scheme is free of filter optimization process and is much simpler. In implementation, the designed half-band filters can be realized as a multi-stage cascaded structure, composed of several short half-band subfilters and delay elements. Since its building elements have trivial coefficients with short wordlengths, the proposed structure for half-band filters has low complexity and low coefficient dynamic range. Thus it is suitable for finite-precision implementation. Furthermore, the structure is highly modular, repetitive in all stages, and suitable for VLSI implementation.
An efficient direct digital frequency synthesizer based on two-level table lookup
(2001)
Chih, JC
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Chou, JY
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Chen, SG
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交大名義發表
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National Chiao Tung University
This paper proposes a new direct digital frequency synthesizer (DDFS). It has the merits of high speed, low complexity and high spectrum purity [1], [2]. It is based on the Taylor's expansion method for sinusoidal and cosine functions, combined with a two-level table-lookup algorithm. The new DDFS is efficient, with a small table size and low computational complexity. In all, this new DDFS needs three lookup tables, each of size 2(N/4), which is smaller than the other table-lookup methods, such as Madisetti, et al., (of size 2(N/3)) [3], [4]. The DDFS is non-recursive, which is free of error-propagation problem inherently in the recursive DDFS's. For N=16-bits example, simulation shows that the new DDFS has a high SFDR (spurious free dynamic range) of 100 dBc.
An efficient memory-based FFT architecture
(2003)
Chang, CK
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Hung, CP
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes an efficient memory-based radix-2 FFT architecture, which greatly improves the memory-based FFT [5], [6] by reducing 50% memory size requirement, while maintaining a simple address generator. Specifically the memory size is reduced to 1.25N words. In addition, the multiplier utilization rate is 100%.
An efficient modified Phong shading algorithm & its low-complexity realization
(2002)
Lai, MH
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Yu, MF
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A modified mixing shading algorithm is proposed, which costs much less operations than that of Phong shading algorithm. Based on the algorithm, a low-complexity shading engine is designed. The shading engine is performed in log space, using low-complexity logarithm and anti-log algorithms. The algorithms are combinations of interpolation algorithm using Taylor's expansion and table-lookup operations. This results in small table size, low complexity and high operation speed. Based on EDA tool simulations, the log-space engine can achieve a high clock rate of 450MHz and a fill rate up to 117.5M pixels/second, with total gate count of 12061.
Design of a rule-based continuous process controller using modified IDEF0 methodology
(1997-09-01)
Chen, SG
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Wu, MZ
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Li, RK
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工業工程與管理學系
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Department of Industrial Engineering and Management
This article proposes a new method to design a rule-based Continuous Process (CP) controller. This approach adopts Modified IDEF0 (MI) diagrams as a graphical representation of production rules. Initially, the material flows or functional requirements for the CP are specified by synthesizing the MI diagram primitives. The control flows for the CP are then created by a number of transformation rules. The MI diagrams are therefore transformed to the Final MI (FMI) diagrams which can be directly transformed to production rules. The fact that production rules are created by systematical transformation eliminates any redundant, contradictory, or unnecessary rules. The simulation approach can verify the consistency of the designed CP controller. Thus, a feasible rule-based CP controller can be systematically developed. An illustrative gas transmission system is examined with three manufacturing policies, i.e. Proportional plus Integral plus Derivative (PID) control, Neural control and Fuzzy control. The results indicate that all of these policies are feasible in applying the proposed method. This method not only provides graphical representations to construct well-organized production rules, but also includes a systematical transformation of the control flows for a CP controller.
Design of a rule-based continuous process controller using modified IDEF0 methodology
(1997-09-01)
Chen, SG
;
Wu, MZ
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Li, RK
;
工業工程與管理學系
;
Department of Industrial Engineering and Management
This article proposes a new method to design a rule-based Continuous Process (CP) controller. This approach adopts Modified IDEF0 (MI) diagrams as a graphical representation of production rules. Initially, the material flows or functional requirements for the CP are specified by synthesizing the MI diagram primitives. The control flows for the CP are then created by a number of transformation rules. The MI diagrams are therefore transformed to the Final MI (FMI) diagrams which can be directly transformed to production rules. The fact that production rules are created by systematical transformation eliminates any redundant, contradictory, or unnecessary rules. The simulation approach can verify the consistency of the designed CP controller. Thus, a feasible rule-based CP controller can be systematically developed. An illustrative gas transmission system is examined with three manufacturing policies, i.e. Proportional plus Integral plus Derivative (PID) control, Neural control and Fuzzy control. The results indicate that all of these policies are feasible in applying the proposed method. This method not only provides graphical representations to construct well-organized production rules, but also includes a systematical transformation of the control flows for a CP controller.
Design of a rule-based flexible manufacturing system controller using modified IDEF0 methodology
(1997-10-01)
Chen, SG
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Wu, MZ
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Li, RK
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工業工程與管理學系
;
Department of Industrial Engineering and Management
This article proposes a new method to design a rule-based FMS controller. This approach adopts modified IDEFO (MI) diagrams as a graphical representation of the production rules. Initially, the material flows or functional requirements for the FMS are specified by synthesizing the MI diagram primitives. The control flows for the FMS are then created by a number of transformation rules. The manufacturing policy, e.g. deadlock avoidance policy, is also specified and attached. The MI diagrams are therefore transformed to the final MI (FMI) diagrams which can be directly transformed to the production rules. Thus, a concise rule-based FMS controller is developed. The fact that the production rules are created by systematic transformation eliminates any redundant, contradictory, or unnecessary rules. Two approaches can verify the consistency of the designed FMS controller. The controlled Petri net approach can be adopted for verifying a small system, while a simulation approach is preferable for verifying a large system. By iterating the process, a feasible rule-based FMS controller can be systematically developed. This method not only provides graphical representations to construct well-organized production rules, but also includes a systematic transformation of the control flows for an FMS controller.
Design of an efficient variable-length FFT processor
(2004)
Hung, CP
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Chen, SG
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Chen, KL
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an efficient variable-length FFT processor architecture suitable for multi-mode and multi-standard OFDM communication systems. The FFT processor is based on radix-2(2) DIF FFT algorithm and also supports non-power-of-4 FFT computation. The design contains an efficient processing element (PE), which can execute radix-2(2) butterfly (BF) operations, as well as radix-2 BF operations. Moreover, in order to achieve high-performance variable-length FFT operations and data accesses, an efficient variable-length address generator and twiddle factor generator are designed. The design has the merits of low complexity and high speed performance. The designs consider seven different FFT lengths including 64, 256, 512, 1024, 2048, 4096, and 8192 points, which cover all the required FFT lengths by 802.1.1a, 802.16a, DAB, DVB-T, VDSL and ADSL.
Design of finite-word-length FIR filters with least-squares error
(2000-08-01)
Kao, YA
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Chen, SG
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a new algorithm for designing finite word length linear-phase FIR filters. The new algorithm produces finite-precision least-squares error (LSE) solutions with much reduced search time than the brute-force full search algorithm. It is different from the full search algorithm that tries all possible combinations directly. The new algorithm utilizes geometric properties of a hyper-space to pinpoint potential solutions in a much more restricted way. Accordingly, a much smaller search space is generated. (C) 2000 Elsevier Science B.V. All rights reserved.
Design of QMF banks based on derivative information
(1999-10-01)
Kao, MC
;
Chen, SG
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New L-2 objective functions for the design of quadrature mirror filter (QMF) banks are proposed. They are based on the derivative information of the reconstruction error Simple and explicit matrix-form formulas for the proposed objective functions are derived. Efficient design methods are proposed by incorporating a separability technique into the derived optimality conditions on prototype filters. The proposed design methods need only solve linear equation iteratively without nonlinear optimisation. Design examples demonstrate that good low-delay QMF banks and linear-phase QMF banks can be obtained in only a few iterations. Compared with the conventional approach, the new approach leads to QMF banks with larger stopband attenuation and smaller reconstruction errors.
Efficient channel estimation based on discrete cosine transform
(2003)
Yeh, YH
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Chen, SG
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Channel impairment caused by multi-path reflections can deeply degrade the transmission efficiency in wireless communication systems. Based on the property of the channel frequency response and the concept of interpolation, in this paper a DCT-based pilot-aided channel estimator for orthogonal frequency division multiplexing is proposed. This approach can mitigate the aliasing effect in the DFT-based channel estimator when there is nonsample-spaced path delay. Compared with DFT-based estimator, DCT-based estimator significantly improves the performance with a comparable complexity. In addition, a noise reduction scheme is introduced and combined with the estimator. In implementation, the DCT-based estimator has the advantages of utilizing mature fast DCT algorithms and compatible FFT algorithms, which is favorable to other matrix-based channel estimation methods.
Fast CORDIC algorithm based on a new recoding scheme for rotation angles and variable scale factors
(2003-01-01)
Chih, JC
;
Chen, SG
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a new rotation mode CORDIC algorithm, which considerably reduces the iteration number. It is achieved by combining several design techniques. Particularly, a new table-lookup recoding scheme for rotation angles and variable scale factors is developed to reduce the iteration numbers for rotation and scale factor compensation. By addressing the MSB parts of the residual rotation angles to a lookup table, two micro rotation angles are retrieved that in combination best matches the MSB parts. We also combine the leading-one bit detection operations for residual rotation angles, to skip unnecessary rotations. The resulting problems of variable scale factors are then solved by our previous fast decomposition and compensation algorithm (C.C. Li and S. G. Chen, in Proceedings of 1996 IEEE International Symposium Circuits and Systems, May 1996, Atlanta, USA, pp. 264-267; C.C. Li and S.G. Chen, in Proceedings of 1997 IEEE International Conference on Acoustic, Speech and Signal Processing, Munich, 1997, Germany, pp. 639-642). To further reduce the iteration number of scale factor compensation, we again apply the mentioned residual recoding technique and the leading-one bit detection scheme to the fast variable scale factor algorithm. Those techniques collectively reduce the iteration number significantly. Simulations show that in average the new design needs only 9.78 iterations to generate results with 22-bit accuracy, including all the iterations for rotations and scale factor compensations. Statistically, the total iteration number is less than n/2 for results with n-bit accuracy. The introduced extra table size is of the same order of magnitude as that for the angle set {tan(-1) 2(-i), i = 0, 1,..., n}, required by general CORDIC algorithms. The new recoding scheme can be applied to other elementary function such as division and square-root functions.
Low-complexity, perfect reconstruction FIR QMF bank
(1998-07-23)
Chen, SG
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Kao, MC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A low-complexity, perfect reconstruction quadrature mirror filter (QMF) bank is proposed, which requires only 50% of the multiplications and additions of the existing QMF banks per output sample. In addition, the new QMF bank only needs to solve a set of linear equations instead of the commonly required nonlinear optimisation technique for the prototype filter.