Browsing by Author "Chen, Sau-Gee"

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A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard
(2007)
Hung, Jui-Hui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology.
A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
(2015)
Davila, Henry Lopez
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Liu, Chun-Yi
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Liu, Wei-Chang
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Huang, Shen-Jui
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Jou, Shyh-Jye
This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-2(3) architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm(2).
A Blind Fine Synchronization Scheme for SC-FDE Systems
(2014-01-01)
Lin, Ying-Tsung
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This work presents a blind fine synchronization scheme, which estimates and compensates residual carrier-frequency offset (RCFO) and symbol timing offset (STO), for single-carrier frequency-domain equalization (SC-FDE) systems. Existing fine synchronization schemes for SC-FDE systems rely on time-domain unique words (UW) sequences as reference signals to assure the estimation accuracy, at the cost of decreased system throughput. The proposed technique, named simplified weighted least-square method for single-carrier systems (SWLS-SC), combines the decision feedback structure and SWLS estimator for OFDM systems. Together with specifically derived weighting factors, it has much better estimation accuracy than the well-known linear least-square (LLS) method for SC-FDE systems, and its BER performance can approach that of the ideal synchronization condition. The proposed technique is more effective than existing techniques, in terms of both performance and throughput. Theoretical estimation bounds are also derived to verify the effectiveness of the proposed method.
A Blind Maximum-SINR Synchronization Technique for OFDM Systems
(2008)
Chin, Wen-Long
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This work presents a blind synchronizer for orthogonal frequency-division multiplexing (OFDM) systems based on signal-to-interference-and-noise-ratio (SINR) maximization. Due to the incurred losses from inter-symbol interference (ISI) and inter-carrier interference (ICI) introduced by synchronization errors, the SINR of the received data drops drastically. By taking advantage of this characteristic, both the symbol time and carrier frequency offsets are intuitively estimated by maximizing the SINR metric. For the SINR metric, we propose a blind SINR estimation, which does not need prior knowledge of the channel profiles and transmitted data. As such, the proposed maximum-SINR (MSINR) synchronization algorithm is non-data-aided (NDA) so that the transmission efficiency can be improved. Moreover, to reduce the computational complexity, the early-late gate (ELG) technique is proposed for the implementation of the synchronizer. Simulation results exhibit better performance for the MSINR algorithm than conventional techniques in multipath fading channels.
A Blind Synchronizer for OFDM Systems Based on SINR Maximization in Multipath Fading Channels
(2009-02-01)
Chin, Wen-Long
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a blind synchronizer for orthogonal frequency-division multiplexing (OFDM) systems based on signal-to-interference-and-noise ratio (SINR) maximization. Due to the incurred losses from intersymbol interference (ISI) and intercarrier interference (ICI) introduced by synchronization errors, the SINR of the received data drastically drops. By taking advantage of this characteristic, both the symbol time and carrier frequency offsets are intuitively estimated by maximizing the SINR metric. For the SINR metric, two blind SINR estimations are investigated. The estimations do not need prior knowledge of the channel profiles and transmitted data. As such, the proposed maximum SINR (MSINR) synchronization algorithm is nondata aided so that the transmission efficiency can be improved. Moreover, to reduce the computational complexity, the early-late gate technique is proposed for the implementation of the synchronizer. Simulation results exhibit better performance for the MSINR algorithm than conventional techniques in multipath fading channels.
A Data Detection Scheme for Single-Carrier Block Transmission Using Sphere Decoding Algorithm
(2010)
Lin, Ying-Tsung
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Kuo, Chia-Hsun
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Chen, Sau-Gee
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Fang, Wai-Chi
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電子工程學系及電子研究所
In this paper, an efficient sphere decoding algorithm (SDA) applied to solve the inter-symbol-interference (ISI) data detection problem is proposed. This proposed algorithm takes advantages of the SDA to obtain the solution close to ML solution with the simplified K-best tree search method for the ISI data detection under ISI effect. Compared with the frequency-domain MMSE or Zero-Forcing equalization techniques for SCBT (Single-Carrier Block Transmission) systems, this algorithm can perform at least 1.5dB better than frequency-domain equalizers under the environment of randomly generated channel impulse responses.
A Fast Systematic Optimized Comparison Algorithm for CNU Design of LDPC Decoders
(2011-11-01)
Hung, Jui-Hui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This work first investigates two existing check node unit (CNU) architectures for LDPC decoding: self-message-excluded CNU (SME-CNU) and two-minimum CNU (TM-CNU) architectures, and analyzes their area and timing complexities based on various realization approaches. Compared to TM-CNU architecture, SME-CNU architecture is faster in speed but with much higher complexity for comparison operations. To overcome this problem, this work proposes a novel systematic optimization algorithm for comparison operations required by SME-CNU architectures. The algorithm can automatically synthesize an optimized fast comparison operation that guarantees a shortest comparison delay time and a minimized total number of 2-input comparators. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. As a result, the proposed design significantly reduces the required number of comparison operations, compared to conventional SME-CNU architectures, under the condition that both designs have the same speed performance. Besides, our preliminary hardware simulations show that the proposed design has comparable hardware complexity to low-complexity TM-CNU architectures.
A High-Parallelism Memory-Based FFT Processor with High SQNR and Novel Addressing Scheme
(2016)
Huang, Shen-Jui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an area-efficient memory-based FFT processor for long FFT lengths. To achieve high throughput, radix-4(2) FFT algorithm is adopted to reduce number of FFT stages. For low-complexity realization of the main butterfly processing element, a folded-by-2 scheme along with an optimized scheduling is designed. Variable FFT lengths (i.e., 1024 similar to 32768 points) can be supported through flexible switch configurations. Moreover, a conflict-free memory addressing scheme is devised to support 16-way parallel and normal-order data input/output without re-ordering buffers. An optimized block floating-point (BFP) scheme is employed for long-length FFT operations. The EDA synthesis results with TSMC-90nm process show that the area of proposed FFT processor is 2.98 mm(2), and the power consumption is 29 mW @160MHz clock frequency. The SQNR performance is over 70dB for all supported FFT lengths with 16-bit wordlength.
A High-Performance Multibit-Flipping Algorithm for LDPC Decoding
(2009)
Hung, Jui-Hui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
For LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. This paper introduces the concepts of low correlation search and culprit vote to further improve the efficiency of the existing BF algorithms. High decoding performances and low iteration number are achieved by flipping those bits with low correlation as much as possible and introducing an additional syndrome vote procedure. As a result, the proposed algorithm can achieve significant decoding performance which is very close to the min-sum algorithm (MSA) but with much lower computation complexity.
A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems
(2012-08-01)
Huang, Shen-Jui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
"This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is mm, and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation."
A joint synchronization algorithm for OFDM systems
(2007)
Chin, Wen-Long
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Chen, Sau-Gee
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Chen, Chih-Liang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This work presents a joint maximum-likelihood (ML) synchronization algorithm for symbol time (ST) offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) for OFDM systems. Unlike most existing techniques which are time-domain approaches considering only AWGN and/or static multipath conditions, the proposed algorithm is developed in frequency-domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of STO, CFO and SCFO is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. Based on the function, a joint ML algorithm is proposed. The joint algorithm is both efficient and robust, because the three main synchronization issues are treated altogether. Simulation results exhibit high performances in time-variant multipath fading channels.
A Low-Complexity High-Performance Decoding Algorithm for Fixed-Point LDPC Decoders
(2008)
Hung, Jui-Hui
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The bit-error-rate (BER) performance of an LDPC decoding algorithm will be seriously degraded when the algorithm is realized with fixed-point implementation in practical applications, due to the introduced quantization errors and rounding errors. To remedy the problem, this paper proposes an improved min-sum algorithm (MSA), called CMVP algorithm. It achieves better performances than the popular min-sum algorithm (MSA), under the condition of the same fixed-point precision. Besides, the hardware overhead of the new algorithm over conventional MSA is small. On the other hand, under the condition of comparable performances, MSA algorithm needs a higher fixed-point precision and hardware costs than the new CMVP algorithm, according to the simulations and hardware synthesis results. The new algorithm also works well in a wide range of code rates and code lengths.
A Low-Complexity Minimum-Interference Symbol Time Estimation for OFDM Systems
(2009-05-01)
Chin, Wen-Long
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Conventional symbol time (ST) synchronization algorithms for orthogonal frequency-division multiplexing (OFDM) systems are mostly based on the maximum correlation result of the cyclic prefix. Due to the channel effect, the estimated ST is not accurate enough. Hence, one needs to further identify the channel impulse response (CIR) so as to obtain a better ST estimation. Overall, the required computational complexity is high because it involves time-domain (TD) correlation operations, as well as the fast Fourier transform (FFF) and inverse FFT (IFFT) operations. In this work. without the FFT/IFFT operations and the knowledge of CIR, a low-complexity TD ST estimation is proposed. We first characterize the frequency-domain (FD) interference effect. Based on the derivation, the new method locates the symbol boundary at the sampling point with the minimum interference in the FD (instead of the conventional maximum TD correlation result). Moreover. to reduce the computational complexity, the proposed FD minimum-interference (MI) metric is converted to a low-complexity TD metric by utilizing Parseval's theorem and the sampling theory. Simulation results exhibit good performance for the proposed algorithm in multipath fading channels.
A Low-Complexity Mixed-Radix FFT Rotator Architecture
(2018-01-01)
Tsai, Wei-Lun
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Chen, Sau-Gee
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Huang, Shen-Jui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
FFT-based OFDM and SC-FDMA transmission technologies have been widely adopted in most advanced telecommunication systems. For future 5G mobile communication systems, FFT again is expected to play very crucial roles. As such, design of FFT processors with unprecedentedly high performance has become a hard challenging problem that must be overcome. Among the components of an FFT processor, the rotator composed of ROMs and multipliers for twiddle factor multiplications take up the most area and power consumption. In order to reduce the cost, a reconfigurable multiplier-less and ROM-less rotator design approach is proposed in this paper. This approach supports both power-of-two and non-power-of-two FFT lengths. It effectively reduces the area by applying a series of decomposition and sharing schemes. An example of a rotator supporting 128-2048/1536-point FFT processor for the 4G LTE system is implemented with TSMC 90nm CMOS technology. Compared to the existing design, this work has 16.75% area reduction and 62.94% power reduction.
A low-complexity symbol time estimation for OFDM systems
(2008)
Chin, Wen-Long
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Chen, Sau-Gee
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Conventional symbol time (ST) synchronization algorithms for orthogonal frequency-division multiplexing (OFDM) systems mostly are based on maximum correlation result of the cyclic prefix. Due to the channel effect, one needs to further identify the channel impulse response (CIR) so as to obtain a better ST estimation. Overall, the required computational complexity is high because it involves correlation operation, as well as the fast Fourier transform (FFT) and inverse FFT (IFFT) operations. In this work, without the FFT/IFFT operations and the knowledge of CIF, a low-complexity time-domain ST estimation is proposed. We first characterize the frequency-domain interference effect as a function of the ST by deriving some analytical equations considering the channel effect. Based on the derivation, the new method locates the symbol boundary at the sampling point with the minimum interference in the frequency-domain. Moreover, for reducing the computational complexity, the proposed frequency-domain minimum-interference metric is converted into a low-complexity time-domain metric by utilizing the Parseval's theorem and the sampling theory. Simulation results exhibit high performances for the proposed algorithm in the multipath fading channels.
A MEMORY-EFFICIENT CONTINUOUS-FLOW FFT PROCESSOR FOR WIMAX APPLICATION
(2012)
Huang, Shen-Jui
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Chen, Sau-Gee
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交大名義發表
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National Chiao Tung University
This paper presents an area-efficient continuous-flow FFT/IFFT processor for Wimax application. Especially, the integration design of FFT processors with other functional blocks is considered according to Wiamx specification. A new memory scheduling scheme targeted for UL-PUSC transmission mode is proposed to reduce about 50% total memory space requirement compared with the conventional ping-pong based approach. In addition, a cascaded and pipelined PE structure is designed for high speed operation. The structure is configurable to support different FFT size efficiently, especially for those non-power-of-8 DFT operations. The EDA synthesis results show that the proposed FFT processor occupies only 1.62 mm(2) area based on TSMC 0.18-um process.
A New Genetics-Aided Message Passing Decoding Algorithm for LDPC Codes
(2012-01-01)
Hung, Jui-Hui
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Lu, Yi-De
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The popular LDPC decoding algorithms based on the message passing (MP) algorithm have high decoding performances. However, they are noticeably inferior to the maximum likelihood (ML) decoding algorithm. This work proposes a genetics-aided message passing (GA-MP) algorithm by applying a new genetic algorithm to MP algorithm. As a result, significantly performance improvement over MP algorithm can be achieved. Besides, compared with other genetic-aided decoding algorithms, the proposed algorithm has much better performances and much lower computational complexity. Simulations show that the decoding performance of GA-MP algorithm can achieve performances very close to the algorithm, while outperform MP algorithm. Besides, its performance will grow proportionally with the generation number without leveling off as observed in conventional MP algorithms, under high SNR condition.
A New Memoryless and Low-latency FFT Rotator Architecture
(2014)
Huang, Shen-Jui
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Chen, Sau-Gee
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents new rotator architecture for FFT computation. The proposed architecture consists of cascaded multiplier-less cells, and each cell stage performs partial twiddle factor multiplications with low-complexity adders and multiplexers. Besides, for further area reduction, each cell is optimized with the technique of common subexpression sharing. Since those twiddle factors involved in computation are realized with multipliers generated on-the-fly by a scheme of coefficient selection, the proposed architecture doesn\'t require memory space to store any twiddle factors. Variable FFT lengths ranging from 64 similar to 32768 points can be supported by flexibly adding or removing some cell stages, depends on FFT length. Compared to CORDIC-based architectures, the proposed architecture has lower latency. The implementation results show that the proposed architecture is area-efficient and is suitable for either pipelined or memory based FFT architectures.
A Novel Pipelined CCK Decoder for IEEE 802.11b System
(2008)
Huang, Shen-Rei
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel decoder for Complementary Code Keying (CCK) modulation is proposed in this work. Compared to the parallel decoder architecture based on Fast Walsh Transform (FWT), the presented pipelined architecture has better hardware sharing and utilization efficiency, as well as smaller area. Its hardware area for finding the maximum decoding output value is minimized by employing a low-complexity on-the-fly comparator that takes advantage of the sequentially incoming chips and the pipelined data flow. Also, the proposed design consumes only 50.6 mu w at 11MHz based on UMC 0.18-mu m process, which is much lower than the conventional FWT-based architecture. Thus it is a low-power and low-area solution for the design of a high-performance 802.11b system.
A Real-Time High-Throughput LDPC Decoder for IEEE 802.3an Standard
(2010)
Hung, Jui-Hui
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Kao, Li-Wei
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Chen, Sau-Gee
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The existing LDPC decoders are mostly based on the belief-propagation (BP) algorithms, due to good BER performances. However, they demand large chip areas. This paper proposes a high-throughput LDPC decoder based on the bit-flipping algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is very close to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with real-time processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.42M gates, 16Gbps and 368mW, respectively, at 500MHz clock rate. Compared with existing BP-based designs, it has much smaller chip area and lower power dissipation, with comparable performances.