Browsing by Author "Chen, Shang-Chun"

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3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
(2018-01-01)
Shen, Wen-Wei
;
Lin, Yu-Min
;
Chen, Shang-Chun
;
Chang, Hsiang-Hung
;
Chang, Tao-Chih
This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-mu m-diameter/ 50-mu m-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-mu m diameter are bonded using three step temperature bonding profile. Further stacked DRAM/ Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.
Characterization of Silicon Photonics Modulator Integration and High Efficiency Testing Platform
(2019-01-01)
Chen, Shang-Chun
;
Wun, Sin-Jhu
;
Hsu, Chih-Hsiang
;
Lin, Chen-Yu
;
Zhang, Jie
We successfully establish a silicon photonics device manufacturing and testing platform in 200mm SOI wafer. We integrate modulator and driver chip to show 30Gbis PAM4 capability. A fully-automatic wafer level characterization process is built up for all optical devices in surface coupling method.