Browsing by Author "Chen, Sheng-Hao"

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Design and Analysis of a CMOS Ratio-Memory Cellular Nonlinear Network (RMCNN) Requiring No Elapsed Time
(2010-06-01)
Wu, Chung-Yu
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Chen, Sheng-Hao
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Wu, Yu
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電機學院
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College of Electrical and Computer Engineering
A CMOS ratio-memory cellular nonlinear network (RMCNN) requiring no elapsed time is proposed. The correlations between any two neighboring cells are stored in the memories. The ratio weights of each cell are generated through a comparison of the four correlations around one cell with the mean value of these four correlations. With this method, the elapsed time required by the previously existing RMCNN algorithm is no longer required and, therefore, the ratio weights can be generated individually. Moreover, the use of multi-dividers can be avoided to make the circuit simple. Based on the proposed algorithm, a CMOS RMCNN chip requiring no elapsed time has been designed and fabricated using TSMC 0.35-mu m 2P4M mixed-signal technology. In the fabricated chip, three test patterns can be learned and recognized.
The Design and Analysis of a CMOS Low-Power Large-Neighborhood CNN With Propagating Connections
(2009-02-01)
Wu, Chung-Yu
;
Chen, Sheng-Hao
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電機學院
;
College of Electrical and Computer Engineering
The design of a large-neighborhood cellular nonlinear network (LN-CNN) with propagating connections is proposed. The propagating connections are utilized to achieve large-neighborhood templates in the shape of diamonds. Based on the propagating connections, each LN-CNN cell can only be connected to neighboring cells without interconnections to farther cells. Thus, it is suitable for very large scale integration implementation. The LN-CNN functions of diffusion, deblurring, and Muller-Lyer illusion are successfully verified. Meanwhile, the functions of erosion and dilation are expanded with the diamond-shaped LN templates. Furthermore, the simple N- and P-type synapses stop all the static current paths so that the do power dissipation can be reduced to only 0.7 mW on standby and 18 mW in operation. An experimental LN-CNN chip with a 20 x 20 array has been fabricated using 0.18-mu m CMOS technology. With the proposed LN-CNN chip, more applications and LN-CNN templates can be studied further.